About QSPI clock setting .

takashitakahash — Thu, 28 May 2015 07:01:41 GMT

Hi community.

I refered VYBRIDRSERIESEC_Rev_7.pdf of p58"9.5.1 QuadSPI timing".

The QSPI_MCR [DDR_EN] a set (to 1b)in the state, if sent the command Programing of "SDR", then

I am recognized as to the operation of p59 of "QuadSPI Output / Write timing (SDR mode)" .

whether I should refer to either the operating conditions of this case,

Of p59 "QuadSPI Output / Write timing (SDR mode)" or of p61 "QuadSPI Output / Write timing (DDR mode)"

Whitch referred to either of?

In operatively "SDR mode", SCK is within the range in the current setting of 69.88MHz in MAX80MHz,
However, when referring to "DDR mode", since the MAX has a 45MHz, it will over the upper limit.

Please teach me SCK setting is no problem at 69.88MHz.

And would you please replay of previous question of ( I want to calculate of ”Read freaquency calculations", "Max read frequency", "Hold timing").

Re: About QSPI clock setting .

alejandrolozan1 — Wed, 17 Jun 2015 22:17:09 GMT

Hi Takashi,

In case you are configuring the QSPI module in SDR you should refer to table 49 which states that the max SCK frequency is 80MHz. Therefore the 69.88MHz won't be an issue as long as you are working in SDR mode.

Best Regards,

Alejandro

topic Re: About QSPI clock setting . in Vybrid Processors

About QSPI clock setting .

Re: About QSPI clock setting .