topic Re: flexbus CLK_RISE to FB_CS_RISE timing in Vybrid Processors https://community.nxp.com/t5/Vybrid-Processors/flexbus-CLK-RISE-to-FB-CS-RISE-timing/m-p/231697#M404 <HTML><HEAD></HEAD><BODY><P>Dear Okubo,</P><P>Since the device mentioned is <SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; font-size: 12.727272033691406px;">MK20FN1M0VLQ12, </SPAN>I am afraid you will have to move this request to the "Kinetis" space (<A _jive_internal="true" href="https://community.nxp.com/community/kinetis">https://community.freescale.com/community/kinetis</A>). This one is only dedicated to the "Vybrid" series (as far as I remember, there should be such an option in upper right corner of the original message web page).</P><P>Plus, just a support person's recommendation - it really helps and expedites the process when a relevant chapter / table / diagram / etc. in our documentation is mentioned in the request.</P><P>Regards, Naoum Gitnik.</P></BODY></HTML> Fri, 25 Oct 2013 17:36:43 GMT naoumgitnik 2013-10-25T17:36:43Z flexbus CLK_RISE to FB_CS_RISE timing https://community.nxp.com/t5/Vybrid-Processors/flexbus-CLK-RISE-to-FB-CS-RISE-timing/m-p/231696#M403 <HTML><HEAD></HEAD><BODY><P>In flexbus, how many seconds (Minimum) is time from the rise of CLK signal to a rise of control signal (FB_CS,FB_OE)?</P><P>About the time from CLK_RISE to FB_CS(FB_OE)_RISE, is it bigger than a demand value of the hold time for data(datasheet Figure 17 "FB5") ?</P><P>device:MK20FN1M0VLQ12</P></BODY></HTML> Fri, 25 Oct 2013 04:00:11 GMT https://community.nxp.com/t5/Vybrid-Processors/flexbus-CLK-RISE-to-FB-CS-RISE-timing/m-p/231696#M403 okubohitoshi 2013-10-25T04:00:11Z Re: flexbus CLK_RISE to FB_CS_RISE timing https://community.nxp.com/t5/Vybrid-Processors/flexbus-CLK-RISE-to-FB-CS-RISE-timing/m-p/231697#M404 <HTML><HEAD></HEAD><BODY><P>Dear Okubo,</P><P>Since the device mentioned is <SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; font-size: 12.727272033691406px;">MK20FN1M0VLQ12, </SPAN>I am afraid you will have to move this request to the "Kinetis" space (<A _jive_internal="true" href="https://community.nxp.com/community/kinetis">https://community.freescale.com/community/kinetis</A>). This one is only dedicated to the "Vybrid" series (as far as I remember, there should be such an option in upper right corner of the original message web page).</P><P>Plus, just a support person's recommendation - it really helps and expedites the process when a relevant chapter / table / diagram / etc. in our documentation is mentioned in the request.</P><P>Regards, Naoum Gitnik.</P></BODY></HTML> Fri, 25 Oct 2013 17:36:43 GMT https://community.nxp.com/t5/Vybrid-Processors/flexbus-CLK-RISE-to-FB-CS-RISE-timing/m-p/231697#M404 naoumgitnik 2013-10-25T17:36:43Z