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    <title>Vybrid ProcessorsのトピックSpecial DDR</title>
    <link>https://community.nxp.com/t5/Vybrid-Processors/Special-DDR/m-p/374230#M3897</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN class="hps"&gt;&lt;SPAN&gt;Dear community.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="hps"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="hps"&gt;&lt;SPAN&gt;Our customer development cluster meter using vybrid.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="hps"&gt;&lt;SPAN&gt;&lt;SPAN class="hps"&gt;Can be display the&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;compressed image&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;using a&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;Special DDR&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;mode&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;in&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;REL function.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="hps"&gt;Drawing&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;specifies&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;the address and&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;size&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;of&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;RLE&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;compressed image&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;data&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;that is on the&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;Flash ROM&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;for&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;Layer # 1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; &lt;SPAN class="hps"&gt;Here, when&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;DCU0_CTRLDESCL0_4.EN&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;field is 1&lt;/SPAN&gt; &lt;SPAN class="atn hps"&gt;(&lt;/SPAN&gt;display &lt;SPAN class="hps"&gt;the&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;Layer # 0) &lt;/SPAN&gt;&lt;SPAN class="hps"&gt;is&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;no problem&lt;/SPAN&gt;, &lt;SPAN class="hps"&gt;But set to&amp;nbsp; &lt;SPAN class="hps"&gt;DCU0_CTRLDESCL0_4.EN&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;field is 0 &lt;/SPAN&gt; &lt;/SPAN&gt;&lt;SPAN class="atn hps"&gt;(&lt;/SPAN&gt;the &lt;SPAN class="hps"&gt;Layer # 0&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;hidden)&lt;/SPAN&gt;&amp;nbsp; &lt;SPAN class="hps"&gt;Drawing&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;will&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;be&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;broken&lt;/SPAN&gt; &lt;SPAN class="atn hps"&gt;(&lt;/SPAN&gt;display &lt;SPAN class="hps"&gt;becomes&amp;nbsp; like &lt;/SPAN&gt;&lt;SPAN class="hps"&gt;sandstorm&lt;/SPAN&gt;).&lt;/P&gt;&lt;P&gt;Condition is&amp;nbsp; &lt;SPAN class="hps"&gt;not&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;drawn&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;to&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;Layer # 0,&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;it is&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;RLE_EN = 0.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="hps"&gt;&lt;/SPAN&gt; &lt;/P&gt;&lt;P&gt;&lt;SPAN class="hps"&gt;Why&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;not &lt;/SPAN&gt;get &lt;SPAN class="hps"&gt;the screen&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;when &lt;/SPAN&gt; &lt;SPAN class="hps"&gt;hide the&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;Layer # 0?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="hps"&gt;&lt;/SPAN&gt; &lt;/P&gt;&lt;P&gt;Would you please &lt;SPAN class="hps"&gt;advice&lt;/SPAN&gt; .&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 13 Feb 2015 08:18:39 GMT</pubDate>
    <dc:creator>takashitakahash</dc:creator>
    <dc:date>2015-02-13T08:18:39Z</dc:date>
    <item>
      <title>Special DDR</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Special-DDR/m-p/374230#M3897</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN class="hps"&gt;&lt;SPAN&gt;Dear community.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="hps"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="hps"&gt;&lt;SPAN&gt;Our customer development cluster meter using vybrid.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="hps"&gt;&lt;SPAN&gt;&lt;SPAN class="hps"&gt;Can be display the&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;compressed image&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;using a&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;Special DDR&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;mode&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;in&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;REL function.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="hps"&gt;Drawing&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;specifies&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;the address and&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;size&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;of&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;RLE&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;compressed image&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;data&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;that is on the&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;Flash ROM&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;for&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;Layer # 1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; &lt;SPAN class="hps"&gt;Here, when&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;DCU0_CTRLDESCL0_4.EN&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;field is 1&lt;/SPAN&gt; &lt;SPAN class="atn hps"&gt;(&lt;/SPAN&gt;display &lt;SPAN class="hps"&gt;the&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;Layer # 0) &lt;/SPAN&gt;&lt;SPAN class="hps"&gt;is&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;no problem&lt;/SPAN&gt;, &lt;SPAN class="hps"&gt;But set to&amp;nbsp; &lt;SPAN class="hps"&gt;DCU0_CTRLDESCL0_4.EN&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;field is 0 &lt;/SPAN&gt; &lt;/SPAN&gt;&lt;SPAN class="atn hps"&gt;(&lt;/SPAN&gt;the &lt;SPAN class="hps"&gt;Layer # 0&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;hidden)&lt;/SPAN&gt;&amp;nbsp; &lt;SPAN class="hps"&gt;Drawing&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;will&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;be&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;broken&lt;/SPAN&gt; &lt;SPAN class="atn hps"&gt;(&lt;/SPAN&gt;display &lt;SPAN class="hps"&gt;becomes&amp;nbsp; like &lt;/SPAN&gt;&lt;SPAN class="hps"&gt;sandstorm&lt;/SPAN&gt;).&lt;/P&gt;&lt;P&gt;Condition is&amp;nbsp; &lt;SPAN class="hps"&gt;not&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;drawn&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;to&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;Layer # 0,&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;it is&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;RLE_EN = 0.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="hps"&gt;&lt;/SPAN&gt; &lt;/P&gt;&lt;P&gt;&lt;SPAN class="hps"&gt;Why&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;not &lt;/SPAN&gt;get &lt;SPAN class="hps"&gt;the screen&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;when &lt;/SPAN&gt; &lt;SPAN class="hps"&gt;hide the&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;Layer # 0?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="hps"&gt;&lt;/SPAN&gt; &lt;/P&gt;&lt;P&gt;Would you please &lt;SPAN class="hps"&gt;advice&lt;/SPAN&gt; .&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 13 Feb 2015 08:18:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Special-DDR/m-p/374230#M3897</guid>
      <dc:creator>takashitakahash</dc:creator>
      <dc:date>2015-02-13T08:18:39Z</dc:date>
    </item>
    <item>
      <title>Re: Special DDR</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Special-DDR/m-p/374231#M3898</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Takashi,&lt;/P&gt;&lt;P&gt;It seems, that you show layer under Layer # 0. It point to empty memory, I think.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;Vilem&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 17 Feb 2015 08:12:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Special-DDR/m-p/374231#M3898</guid>
      <dc:creator>VilemZ</dc:creator>
      <dc:date>2015-02-17T08:12:51Z</dc:date>
    </item>
    <item>
      <title>Re: Special DDR</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Special-DDR/m-p/374232#M3899</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear Vilem.&lt;/P&gt;&lt;P&gt;Thank you for your replay.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But I think , &lt;SPAN class="hps"&gt;When use the &lt;/SPAN&gt;&lt;SPAN class="hps"&gt;layer #0&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;view&lt;/SPAN&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;SPAN&gt;Layer&lt;/SPAN&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;SPAN class="highlight"&gt;# 0)&lt;/SPAN&gt;&lt;/SPAN&gt;&amp;nbsp; is&amp;nbsp; &lt;SPAN class="hps"&gt;no&lt;/SPAN&gt;&lt;SPAN class="hps"&gt; problem&lt;/SPAN&gt; ,&lt;SPAN class="hps"&gt;if dose not use the layer# 0&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;SPAN&gt;hidden Layer # 0.&lt;/SPAN&gt;&lt;SPAN class="highlight"&gt;)&lt;/SPAN&gt; is &lt;/SPAN&gt; &lt;SPAN class="hps"&gt;problem&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;occurs.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt; I dont think&amp;nbsp; Layer # 0. It point to empty memory.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="hps"&gt;Have you&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;considered&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;the&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;other&lt;/SPAN&gt;?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="hps"&gt;&lt;/SPAN&gt; &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 18 Feb 2015 08:01:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Special-DDR/m-p/374232#M3899</guid>
      <dc:creator>takashitakahash</dc:creator>
      <dc:date>2015-02-18T08:01:22Z</dc:date>
    </item>
    <item>
      <title>Re: Special DDR</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Special-DDR/m-p/374233#M3900</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Takashi,&lt;/P&gt;&lt;P&gt;Yes, I thought, that layer under Layer # 0 was corrupted. Not Layer # 0. But when you hide Layer # 0, you want see something else. And it is corrupted. Maybe it is point to bad memory (bad pointer or address). &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;Vilem&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 18 Feb 2015 08:09:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Special-DDR/m-p/374233#M3900</guid>
      <dc:creator>VilemZ</dc:creator>
      <dc:date>2015-02-18T08:09:06Z</dc:date>
    </item>
    <item>
      <title>This an automatic process.  We are marking this post as s...</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Special-DDR/m-p/1136539#M6064</link>
      <description>&lt;B&gt;This an automatic process.&lt;/B&gt;&lt;BR /&gt;&lt;BR /&gt;
We are marking this post as solved, due to the either low activity or any reply marked as correct.&lt;BR /&gt;&lt;BR /&gt;
If you have additional questions, please create a new post and reference to this closed post.&lt;BR /&gt;&lt;BR /&gt;
NXP Community!</description>
      <pubDate>Thu, 03 Sep 2020 15:42:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Special-DDR/m-p/1136539#M6064</guid>
      <dc:creator>CommunityBot</dc:creator>
      <dc:date>2020-09-03T15:42:24Z</dc:date>
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