Vybrid Processors中的主题 Re: Sample-based profiling https://community.nxp.com/t5/Vybrid-Processors/Sample-based-profiling/m-p/360087#M3701 <HTML><HEAD></HEAD><BODY><P>Never mind. I am going to "manually" generate the program counter samples by periodically reading DBGPCSR through the debugger.</P></BODY></HTML> Thu, 02 Oct 2014 06:06:54 GMT keanmariotti 2014-10-02T06:06:54Z Sample-based profiling https://community.nxp.com/t5/Vybrid-Processors/Sample-based-profiling/m-p/360086#M3700 <HTML><HEAD></HEAD><BODY><P>I would like to profile the A5 core of my Vybrid VF6xx by periodically sampling the program counter (PC).</P><P></P><P>I see from the "ARMv7-M architecture reference manual" and the "Vybrid reference manual (section 20.9)" that the M4 core provides a Data Watchpoint and Trace (DWT) unit that can be configured to sample the PC at regular intervals. The sampled PC can then be streamed to the SWO interface which I can read with my debugger. This is exactly what I would like to do with the A5 core, instead of the M4.</P><P></P><P>Is there any way to achieve the same result (stream of PC information to SWO) with the A5 core? As far as I understand the A5 does provide a program counter sampling register (DBGPCSR), but lacks of a mechanism to stream it. Am I wrong?</P><P></P><P>Best regards</P><P>Kean Mariotti</P></BODY></HTML> Wed, 01 Oct 2014 08:55:46 GMT https://community.nxp.com/t5/Vybrid-Processors/Sample-based-profiling/m-p/360086#M3700 keanmariotti 2014-10-01T08:55:46Z Re: Sample-based profiling https://community.nxp.com/t5/Vybrid-Processors/Sample-based-profiling/m-p/360087#M3701 <HTML><HEAD></HEAD><BODY><P>Never mind. I am going to "manually" generate the program counter samples by periodically reading DBGPCSR through the debugger.</P></BODY></HTML> Thu, 02 Oct 2014 06:06:54 GMT https://community.nxp.com/t5/Vybrid-Processors/Sample-based-profiling/m-p/360087#M3701 keanmariotti 2014-10-02T06:06:54Z