topic Vybrid TWR-VF65 debug in Vybrid Processors https://community.nxp.com/t5/Vybrid-Processors/Vybrid-TWR-VF65-debug/m-p/354755#M3635 <HTML><HEAD></HEAD><BODY><P>Dear Vybrid users,</P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P>TWR-VF65 rev. H can be debugged by:</P><UL><LI>on-board OpenSDA. CMSIS-DAP application needed. Default Virtual serial port application loaded. CMSIS-DAP + Virtual serial port application attached for your convenience (DS-5 5.19 and higher needed)<UL></UL></LI></UL><P>or</P><UL><LI>external debugger connected to J5 (J-Link,Lauterbach, DSTREAM,....) or J11 (Lauterbach, DSTREAM).</LI></UL><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P>When used external debugger and Tower System is powered from the primary elevator then <STRONG>OpenSDA circuit blocks SWD/JTAG lines</STRONG>.</P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P>To avoid this:</P><UL><LI>power Tower System from J3</LI></UL><P>or</P><UL><LI><STRONG>populate resistor R161 10k</STRONG> which is default DNP - bottom side, between U14 and U13 - see the picture below:</LI></UL><P><span class="lia-inline-image-display-wrapper" image-alt="15220_15220.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/119986iB3471E7C6BC45DB5/image-size/large?v=v2&amp;px=999" role="button" title="15220_15220.png" alt="15220_15220.png" /></span><span class="lia-inline-image-display-wrapper" image-alt="pastedImage_6.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/46320iBF9B7AF99C02DCFF/image-size/large?v=v2&amp;px=999" role="button" title="pastedImage_6.png" alt="pastedImage_6.png" /></span></P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P>The reason is that when powered from the primary elevator and U3 power is not present then OpenSDA is in reset state - default value of U14D is not set.</P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P>Rev.G of TWR-VF65 has to be powered from U3, so workaround is not applicable here.</P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P>/Jiri</P><P><STRONG>Original Attachment has been moved to: <A _jive_internal="true" href="https://community.nxp.com/docs/DOC-339082">CMSIS-DAP-VSP-FSL-VID-PID.zip</A></STRONG></P></BODY></HTML> Mon, 29 Sep 2014 16:51:53 GMT jiri-b36968 2014-09-29T16:51:53Z Vybrid TWR-VF65 debug https://community.nxp.com/t5/Vybrid-Processors/Vybrid-TWR-VF65-debug/m-p/354755#M3635 <HTML><HEAD></HEAD><BODY><P>Dear Vybrid users,</P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P>TWR-VF65 rev. H can be debugged by:</P><UL><LI>on-board OpenSDA. CMSIS-DAP application needed. Default Virtual serial port application loaded. CMSIS-DAP + Virtual serial port application attached for your convenience (DS-5 5.19 and higher needed)<UL></UL></LI></UL><P>or</P><UL><LI>external debugger connected to J5 (J-Link,Lauterbach, DSTREAM,....) or J11 (Lauterbach, DSTREAM).</LI></UL><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P>When used external debugger and Tower System is powered from the primary elevator then <STRONG>OpenSDA circuit blocks SWD/JTAG lines</STRONG>.</P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P>To avoid this:</P><UL><LI>power Tower System from J3</LI></UL><P>or</P><UL><LI><STRONG>populate resistor R161 10k</STRONG> which is default DNP - bottom side, between U14 and U13 - see the picture below:</LI></UL><P><span class="lia-inline-image-display-wrapper" image-alt="15220_15220.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/119986iB3471E7C6BC45DB5/image-size/large?v=v2&amp;px=999" role="button" title="15220_15220.png" alt="15220_15220.png" /></span><span class="lia-inline-image-display-wrapper" image-alt="pastedImage_6.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/46320iBF9B7AF99C02DCFF/image-size/large?v=v2&amp;px=999" role="button" title="pastedImage_6.png" alt="pastedImage_6.png" /></span></P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P>The reason is that when powered from the primary elevator and U3 power is not present then OpenSDA is in reset state - default value of U14D is not set.</P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P>Rev.G of TWR-VF65 has to be powered from U3, so workaround is not applicable here.</P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P>/Jiri</P><P><STRONG>Original Attachment has been moved to: <A _jive_internal="true" href="https://community.nxp.com/docs/DOC-339082">CMSIS-DAP-VSP-FSL-VID-PID.zip</A></STRONG></P></BODY></HTML> Mon, 29 Sep 2014 16:51:53 GMT https://community.nxp.com/t5/Vybrid-Processors/Vybrid-TWR-VF65-debug/m-p/354755#M3635 jiri-b36968 2014-09-29T16:51:53Z