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    <title>Vybrid ProcessorsのトピックVYbrid FPU</title>
    <link>https://community.nxp.com/t5/Vybrid-Processors/VYbrid-FPU/m-p/349155#M3506</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I can't seem to make the FPU in the VYBrid work.&lt;/P&gt;&lt;P&gt;If I enable it, the cpu hangs on the first FPU instruction.&lt;/P&gt;&lt;P&gt;I'm only setting --fpu-VFPv4 in the DS-5 code generation page.&lt;/P&gt;&lt;P&gt;I get code, but the board instantly crashes, and must be power off to reset; the reset button has not effect.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Any clues?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 11 Aug 2014 04:06:39 GMT</pubDate>
    <dc:creator>jackdean</dc:creator>
    <dc:date>2014-08-11T04:06:39Z</dc:date>
    <item>
      <title>VYbrid FPU</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/VYbrid-FPU/m-p/349155#M3506</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I can't seem to make the FPU in the VYBrid work.&lt;/P&gt;&lt;P&gt;If I enable it, the cpu hangs on the first FPU instruction.&lt;/P&gt;&lt;P&gt;I'm only setting --fpu-VFPv4 in the DS-5 code generation page.&lt;/P&gt;&lt;P&gt;I get code, but the board instantly crashes, and must be power off to reset; the reset button has not effect.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Any clues?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 11 Aug 2014 04:06:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/VYbrid-FPU/m-p/349155#M3506</guid>
      <dc:creator>jackdean</dc:creator>
      <dc:date>2014-08-11T04:06:39Z</dc:date>
    </item>
    <item>
      <title>Re: VYbrid FPU</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/VYbrid-FPU/m-p/349156#M3507</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Fore some weird reason DS-5 doesn't care about enabling FPU. You need to have something like this in your startup file:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MRC p15, 0, r0, c1, c1, 2&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ORR r0, r0, #(3&amp;lt;&amp;lt;10)&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ; //enable fpu&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MCR p15, 0, r0, c1, c1, 2&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ;//2. Set the CPACR for access to CP10 and CP11:&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MOV r0, #(0xF &amp;lt;&amp;lt; 20)&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MCR p15, 0, r0, c1, c0, 2&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ;//3. Set the FPEXC EN bit to enable the FPU:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MOV R3, #0x40000000&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; VMSR FPEXC, R3&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 11 Aug 2014 12:19:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/VYbrid-FPU/m-p/349156#M3507</guid>
      <dc:creator>kef2</dc:creator>
      <dc:date>2014-08-11T12:19:24Z</dc:date>
    </item>
    <item>
      <title>Re: VYbrid FPU</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/VYbrid-FPU/m-p/349157#M3508</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Edward,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for your reply.&lt;/P&gt;&lt;P&gt;I had this:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ; CPACR is located at address 0xE000ED88&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; LDR.W&amp;nbsp;&amp;nbsp; R0, =0xE000ED88&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ; Read CPACR&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; LDR&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; R1, [R0]&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ; Set bits 20-23 to enable CP10 and CP11 coprocessors&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ORR&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; R1, R1, #(0xF &amp;lt;&amp;lt; 20)&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ; Write back the modified value to the CPACR&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; STR&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; R1, [R0]; wait for store to complete&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; DSB&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ;reset pipeline now the FPU is enabled&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ISB&lt;/P&gt;&lt;P&gt;Which is from ARM. With your suggestion I get this error:&lt;/P&gt;&lt;P&gt;"F:/VYBrid/Whetstone/src/cpu/crt0_armcc.s", line 120: Error: A1854E: Unknown opcode 'VMSR', maybe wrong target CPU?&lt;/P&gt;&lt;P&gt;with&lt;/P&gt;&lt;P&gt;-DTOWER -DARMCC_A5 -I../../../../../src/common -I../../../../../src/drivers/ccm -I../../../../../src/cpu/header/CMSIS -I../../../../../src/cpu/header -I../../../../../src/cpu -I../../../../../src/platforms -I../../../../../src/drivers/ddr -I../../../../../src/drivers/serial -I../../../../../src/drivers/lptmr -I../../../../../src/projects/Whetstone -O0 --cpu=Cortex-A5 --littleend --arm --fpu=vfpv4 -g --diag_suppress=1786&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you again.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;j&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 11 Aug 2014 16:58:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/VYbrid-FPU/m-p/349157#M3508</guid>
      <dc:creator>jackdean</dc:creator>
      <dc:date>2014-08-11T16:58:50Z</dc:date>
    </item>
    <item>
      <title>Re: VYbrid FPU</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/VYbrid-FPU/m-p/349158#M3509</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Oh, I have&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;--cpu=Cortex-A5.neon&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;and am using Neon features as well. &lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 11 Aug 2014 17:59:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/VYbrid-FPU/m-p/349158#M3509</guid>
      <dc:creator>kef2</dc:creator>
      <dc:date>2014-08-11T17:59:06Z</dc:date>
    </item>
    <item>
      <title>Re: VYbrid FPU</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/VYbrid-FPU/m-p/349159#M3510</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thank you for your help and input.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 11 Aug 2014 18:38:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/VYbrid-FPU/m-p/349159#M3510</guid>
      <dc:creator>jackdean</dc:creator>
      <dc:date>2014-08-11T18:38:41Z</dc:date>
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