Vybrid ProcessorsのトピックRe: Quick Help with GPIO

Quick Help with GPIO

davidpeter — Tue, 26 Nov 2013 19:56:13 GMT

At a little bit of a lost here.. I'm not using MQX just some simple, I thought, GPIO writing and reading. I seems to not clearly under stand the data sheet.

example:

IOMUXC->SINGLE.PTC15 = 0x1D; // set as input with 47K pull up on PTC15

rd = GPIO1->PDIR; // read and bit 28 I think is PTC15 and it should be HIGH

what am I missing..

Thanks

Re: Quick Help with GPIO

billpringlemeir — Tue, 26 Nov 2013 20:46:40 GMT

The PORT CONTROL module must be configured to an interrupt. See section 7.3 of the manual. Is PTC the same as GPIO1? I think it should be GPIO2 for PTC. Ie, GPIO0-4 gives PT[A-E].

Edit: PTC15 is very weird naming. It is actully RGPIO-60 (60-32=28), so it is GPIO-1 bit 28. Section 8.11.1.1 GPIO Mapping gives an overview of all the PTxNN mappings to the GPIO values. This can be very confusing. The PTxNN are only used for pin naming.

Re: Quick Help with GPIO

naoumgitnik — Tue, 26 Nov 2013 20:54:21 GMT

Hello David,

Without going into details of your HW and SW, it is not enough to just enable a pull-up.

According to 'Chapter 5 Input/Output Multiplexer Controller (IOMUXC)' of 'Vybrid Reference Manual, Rev. 5, 07/2013', quite likely, you will also have to take care of the 'Buffer Enable' and 'Pull / Keep' fields (e.g. see the 'IOMUXC_PTA6 field descriptions' table).

Regards, Naoum Gitnik.

Re: Quick Help with GPIO

davidpeter — Tue, 26 Nov 2013 21:20:46 GMT

Naoum

Thanks, though the port is configured:

IOMUXC->SINGLE.PTC15 = 0x1D

which is 0x1D:

IOMUX_IBE_ENABLED

IOMUX_PUE_ENABLED

IOMUX_PKE_ENABLED

IOMUX_PUS_47KPUP

This config works OK with the two switches GPIO on the Tower VyBrid board and the getting_started code for IAR. I don't see any reference to Port Control. This does not mean I disagree with you guys. I just don't see and code modifying the Port Control

Re: Quick Help with GPIO

naoumgitnik — Tue, 26 Nov 2013 21:31:25 GMT

Good point, Bill!

"7.3.1 General-purpose input

The logic state of each pin is available via the Port Data Input registers, provided the pin is configured for a digital function and the corresponding Port Control and Interrupt module is enabled.

The Port Data Input registers return the synchronized pin state after any enabled digital filter in the Port Control and Interrupt module. The input pin synchronizers are shared with the Port Control and Interrupt module, so that if the corresponding Port Control and

Interrupt module is disabled, then synchronizers are also disabled."

Interestingly enough, "This config works OK with the two switches GPIO on the Tower VyBrid board" for the discussion originator; IMO, something changed in the settings, and quite likely what you mentioned.

Regards, Naoum Gitnik.

Re: Quick Help with GPIO

billpringlemeir — Tue, 26 Nov 2013 22:37:20 GMT

It is possible that the boot ROM changes the PORT registers; especially if the GPIO is a boot config pin. I looked in u-boot and the TimeSys Linux and didn't see a reference to the PORT registers there. Maybe it is in the MQX code on the M4. I didn't check that. Are you using the same or different GPIOs as the tower switches in your bare metal version?

Re: Quick Help with GPIO

davidpeter — Wed, 27 Nov 2013 00:29:33 GMT

Bill,

We are using the switches plus some other GPIO.

Re: Quick Help with GPIO

billpringlemeir — Wed, 04 Dec 2013 22:24:34 GMT

You also need to turn on the clocks. See pg670

CCM_CCGR2[CG41] AIPS0-Slot73 Port A multiplexing control
CCM_CCGR2[CG42] AIPS0-Slot74 Port B multiplexing control
CCM_CCGR2[CG43] AIPS0-Slot75 Port C multiplexing control
CCM_CCGR2[CG44] AIPS0-Slot76 Port D multiplexing control
CCM_CCGR2[CG45] AIPS0-Slot77 Port E multiplexing control

These clocks are listed as disabled by the HAB/ROM (pg832, table 19-5). u-boot seems to gate all the clocks on. Check vybrid/lowlevel_init.S, for some start code.