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    <title>topic Vybrid interrupt input pin in Vybrid Processors</title>
    <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-interrupt-input-pin/m-p/337662#M3304</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;1-Which input pins in the vybrid VF6XX processor (364BGA) can I use for external interruptions?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2-Is there any documentation that link the modules external signals names in the reference manual with the pin names?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/rendy"&gt;rendy&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/josepalazzi-b02602"&gt;josepalazzi-b02602&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/BrunoCastelucci"&gt;BrunoCastelucci&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/bfac"&gt;bfac&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/karinavalencia"&gt;karinavalencia&lt;/A&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 20 Oct 2014 16:49:39 GMT</pubDate>
    <dc:creator>marioturqueti</dc:creator>
    <dc:date>2014-10-20T16:49:39Z</dc:date>
    <item>
      <title>Vybrid interrupt input pin</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-interrupt-input-pin/m-p/337662#M3304</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;1-Which input pins in the vybrid VF6XX processor (364BGA) can I use for external interruptions?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2-Is there any documentation that link the modules external signals names in the reference manual with the pin names?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/rendy"&gt;rendy&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/josepalazzi-b02602"&gt;josepalazzi-b02602&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/BrunoCastelucci"&gt;BrunoCastelucci&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/bfac"&gt;bfac&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/karinavalencia"&gt;karinavalencia&lt;/A&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 20 Oct 2014 16:49:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-interrupt-input-pin/m-p/337662#M3304</guid>
      <dc:creator>marioturqueti</dc:creator>
      <dc:date>2014-10-20T16:49:39Z</dc:date>
    </item>
    <item>
      <title>Re: Vybrid interrupt input pin</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-interrupt-input-pin/m-p/337663#M3305</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Mario,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;You can identify which pins are available as interrupts on the Reference Manual (VYBRIDRM.pdf, rev 7), on "Chapter 5 Signal Multiplexing", you will notice a great part of the pins have as "Alt0" a description of, for example, PTA0 (this means that specific pin is Port A, pin 0), all pin ports can be configured as interrupts. In this same table you can see which pins are available on the specific package you are using.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The registers you need to change in order to configure the interrupts are described also on the Reference Manual, on "&lt;SPAN style="font-size: 10pt; line-height: 1.5em;"&gt;Chapter 7 &lt;/SPAN&gt;&lt;SPAN style="font-size: 10pt; line-height: 1.5em;"&gt;Port Control and Interrupts (PORT)":&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;- "7.6 Functional description" will give you an understanding of the working modes.&lt;/P&gt;&lt;P&gt;- "7.5 Memory map and register definition" will describe what registers needs to be configured.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please notice that PTA0 translates to PORT0_PCR0, as well as PTD3 translates to &lt;SPAN style="font-size: 13.6000003814697px;"&gt;PORT3_PCR3, as examples.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR,&lt;/P&gt;&lt;P&gt;Bruno&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/flaviocaduda"&gt;flaviocaduda&lt;/A&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 21 Oct 2014 09:42:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-interrupt-input-pin/m-p/337663#M3305</guid>
      <dc:creator>bfac</dc:creator>
      <dc:date>2014-10-21T09:42:09Z</dc:date>
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