Vybrid ProcessorsのトピックRe: SAI bus clock selection

SAI bus clock selection

falstaff — Thu, 29 Jan 2015 16:55:11 GMT

Hi,

I tried to verify which clock exactly is slected by the SAI bus clock selection (TCR2[MSEL]=0).

Let's start from the obvious: When I set TCR2[MSEL] = 01, I get the clock defined CCM_CSCMR1[SAIn_CLK_SEL], more over the whole logic including the gate CCM_CSCDR1[SAIn_EN] and the divider CCM_CSCDR1[SAIn_DIV] works as documented in Chapter 9.10.12 SAI clocking.

However, when switching to TCR2[MSEL] = 00, unexpectetly the output clock does not change. Also, when I use the gate from above (CCM_CSCDR1[SAIn_EN]) my bit clock gets disabled too, hence it looks like the two MSEL are actually the same SAIn clocks, as configured in CSCMR1 and friends. Is this really the case or am I missing something? IMHO, the documentation is somewhat unclear if Bus Clock actually really selects the SAIn clock too...

Stefan

Re: SAI bus clock selection

jiri-b36968 — Tue, 03 Feb 2015 15:26:21 GMT

Hi Stefan,

No other setting just TCR2[MSEL] and if TCR2[MSEL]=1 then CCM_CSCMR1 is used:

Please check if TE is enabled. TCR2 register must not be altered when TCSR[TE] is set.

You can also check clocks using 10.2.14 CCM Clock Output Source Register (CCM_CCOSR)

/Jiri

Re: SAI bus clock selection

falstaff — Wed, 04 Feb 2015 09:50:34 GMT

Hi Jiri,

Sorry, maybe I was a bit unclear, but this does not really answer my question. I do get an output clock. my concern is the possible selection using TCR2[MSEL]

My question is: Which clock is used if TCR2[MSEL] is b00. According to the reference manual, chapter 3.11.1.2.3 "SAI transmitter and receiver options for MCLK selection", table Table 3-30, b00 is "Bus Clock". However, it looks like it is the same as when using b01, hence not bus clock, but clock selected by SAIn_CLK_SEL...

Stefan

Re: SAI bus clock selection

jiri-b36968 — Wed, 04 Feb 2015 11:47:36 GMT

Hi Stefan,

if TCR2[MSEL] == 0 then it is bus clock (IPS bus clock), which is 133-166MHz/2 if IPG_CLK_DIV=2

if TCR2[MSEL] == 1 then is used clock defined in CCM_CSCMR1 so it can be External clock, SPDIF clk or PLL4 Main clk.

please check if TE is enabled - TCR2 register must not be altered when TCSR[TE] is set.

/Jiri

Re: SAI bus clock selection

falstaff — Wed, 04 Feb 2015 15:56:56 GMT

Hi Jiri,

I explicitly write a 0x0 to TCSR, then change TCSR[MSEL] to b00, and enable TE again, however, I still get 73.735MHz. I also tried from the reset state, by setting TCSR[MSEL] to 0 before ever enabling the transmitter.

The measured clock with TCSR[MSEL] b00 is 73.725MHz, which seems to be the SAI clock. PLL Audio is at it's default value of 1176MHz divided by the 8 using CCM_CACRR[PLL4_CLK_DIV] and another 2 by the minimal divider of SAI. I would expect 83.3MHz/2 as output on my module (500MHz system clock, 166MHz bus clock => 83.3MHz IPG clock).

Stefan

Re: SAI bus clock selection

alejandrolozan1 — Wed, 04 Feb 2015 22:57:01 GMT

Hi Stefan,

I have been testing the MQX code changing the MSEL values and the example keeps working in the same manner. Then I realized that the MQX driver is using by default the PLL4 as source for the Master clock.

Can you share some example code we can test on our side?

Regards,

Alejandro

Re: SAI bus clock selection

jiri-b36968 — Thu, 05 Feb 2015 14:23:33 GMT

Hi Stefan,

I can try it later, but if you select TCR2[MSEL] == 0 and IPG_CLK_DIV=2 and platform clock is 150MHz then IPB bus clock is 75 MHz. - this is correct.

What is your configuration in TCR2[MSEL] == 1 ?

/Jiri

Re: SAI bus clock selection

falstaff — Thu, 05 Feb 2015 15:57:41 GMT

Hi Alejandro,

I use a altered version of the mainline Linux Kernel driver for SAI, but the relevant part is the same:

https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/sound/soc/fsl/fsl_sai.c#n118

When i set FSL_SAI_CR2_MSEL_BUS, I get the same as when I set FSL_SAI_CR2_MSEL_MCLK1.

As far as I understand, just setting MSEL to bus clock without changing anything should make a difference (given that transmitter is disabled while chaning and enabled afterwards). If your clock don't change to the IPG bus clock (divided by the I2Sx_TCR2[DIV]), then your observation would be the same as my mine: MSEL b00 (bus clock) is essentially the same as MSEL b01 (SAI clock).

Stefan

Re: SAI bus clock selection

falstaff — Thu, 05 Feb 2015 16:16:54 GMT

Hi Jiri,

The platform clock is 166MHz, hence I would epxect ~41.6MHz as output clock (/2 due to IPG, /2 in SAI).

When using TCR2[MSEL] = b01, we use PLL4 main clock at 1176MHz with CCM_CACRR[PLL4_CLK_DIV] divider of 8.

Stefan

Re: SAI bus clock selection

jiri-b36968 — Fri, 06 Feb 2015 12:29:53 GMT

Hi Stefan,

I will try it. Will create test project with clockout and measure it in WW8. If you have code which you can share and which does not work for you - upload it please.

/Jiri

Re: SAI bus clock selection

falstaff — Fri, 06 Feb 2015 14:36:08 GMT

What we use is basically the driver in mainline Linux kernel I pointed to above in the answer to Alejandro. I just tried to use the bus clock instead of the SAI clock.

Re: SAI bus clock selection

karina_valencia — Tue, 17 Mar 2015 16:50:01 GMT

alejandrolozano can you continue with the follow up?

Re: SAI bus clock selection

alejandrolozan1 — Tue, 17 Mar 2015 22:29:48 GMT

Hi falstaff, karinavalencia

Sure, I just tested with MQX and just like Stefan mentioned the MCLK does not change modifyng the MSEL bit.

jiri-b36968 I wonder if you have some baremetal project Stefan and I can use to test and narrow down the possible issue.

Best Regards,

Alejandro

Re: SAI bus clock selection

falstaff — Wed, 18 Mar 2015 09:44:55 GMT

Hi Alejandro,

Sorry, I do not have a bare metal project. This appeared while working on a Linux SAI driver. I also do not have DS-5 development environment setup up to create a bare metal project quickly.

To me, it really looks like a hardware issue...

Stefan

Re: SAI bus clock selection

alejandrolozan1 — Wed, 18 Mar 2015 15:35:01 GMT

Hi Stefan,

I asked jiri-b36968 if there is some validation code we can use as reference. That will help to identify it is a hardware issue. If you do not have DS-5 I can test it for you.

/Alejandro

Re: SAI bus clock selection

karina_valencia — Mon, 23 Mar 2015 18:35:49 GMT

jiri-b36968 any comment?

Re: SAI bus clock selection

jiri-b36968 — Mon, 23 Mar 2015 20:43:07 GMT

Hi Alejandro,

Here is some test code.

Easier way it will be connect debugger and measure it on clockout (CCM module).

/Jiri

Re: SAI bus clock selection

karina_valencia — Mon, 30 Mar 2015 18:29:40 GMT

falstaff can you share the status here?

Re: SAI bus clock selection

falstaff — Tue, 31 Mar 2015 07:09:04 GMT

Sorry, I was not aware that actions from my side are currently required. I do not have DS-5 installed... alejandrolozano can you test the validation code?

Re: SAI bus clock selection

alejandrolozan1 — Tue, 31 Mar 2015 14:59:28 GMT

Hi Stefan and Karina,

In fact I was going to test the validation code Jiri sent, but last week I was swamped.

I will start testing today. I will let you know my findings Stefan.

Best Regards,

Alejandro