topic Enable/Disable L2 Cache in Vybrid Processors

Enable/Disable L2 Cache

adamszalkowski — Thu, 18 Sep 2014 11:46:11 GMT

Is it possible to disable the L2 once it has been enabled by the boot loader? Or is it only possible via e-fuse to avoid initialization during boot? How can I initialize the L2 manually?

Re: Enable/Disable L2 Cache

billpringlemeir — Thu, 18 Sep 2014 18:58:32 GMT

The L2-cache controller is an l2c310_r3p2. The data sheet can be downloaded from the ARM web sight. From the documentation, the base physical address is 0x40006000. The controller is trustzone aware. To access everything, you must be in the secure supervisor modes. The Vybrid configuration has no data banking, no lock down by line/master and no parity. It is 64KB way size with 8 ways. The address 40006100 bit 0 will turn the L2 cache on and off. However, you might need to do some flushing and/or invalidation before doing this.

Edit: Also the MQX version of the cortex-A5 BSP/PSP has some code for manipulating the L2. There is also Linux source and header to handle several ARM L2 designs. The key is the Vybrid L2 register base is 0x40006000; it is in the memory map of the Vybrid software reference manual.

Re: Enable/Disable L2 Cache

naoumgitnik — Thu, 18 Sep 2014 21:08:45 GMT

Dear Adam,

If the cache is not disabled by a fuse, enabling and disabling it is possible by software; if the fuse disables it, software cannot do anything.
What is the exact Vybrid part number you are using, please?

Regards, Naoum Gitnik.

Re: Enable/Disable L2 Cache

adamszalkowski — Mon, 22 Sep 2014 08:11:42 GMT

Hello Naoum,

I'm using the tower board TWR-VF65GS10 (processor is PVF61GS151CMK50).

Regards,

Adam

Re: Enable/Disable L2 Cache

naoumgitnik — Mon, 22 Sep 2014 16:32:40 GMT

Dear Adam,

I only needed the part number to verify how the L2 cache is "fused" on your part, and it looks like it has it enabled.

Regards, Naoum Gitnik.

Re: Enable/Disable L2 Cache

adamszalkowski — Wed, 24 Sep 2014 13:23:50 GMT

Seems like I managed to disable the cache i.e. *(int*)0x40006100) == 0

Anyway, I would like to use the SRAM at 0x3f48xxxx for program memory. Every access to this area aborts.

Re: Enable/Disable L2 Cache

kef2 — Wed, 24 Sep 2014 13:46:45 GMT

See the digit before N letter in part number. 1N - you have L2 cache and no RAM at 0x3f48xxxx , 0N - no L2 cache but 0.5MB RAM at 0x3f480000. You can't map L2 cache RAM to address space anyhow.

Re: Enable/Disable L2 Cache

adamszalkowski — Wed, 24 Sep 2014 13:49:26 GMT

Pity, thanks for the clarification

Re: Enable/Disable L2 Cache

kef2 — Wed, 24 Sep 2014 13:57:32 GMT

Another pity is a memory hole between SYS RAM and GXF RAM. Easy to glue them using MMU and make A5 CPU believing there's no hole. But DMA ... doesn't mind MMU.