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    <title>topic Binary Loading : TCM and OCRAM in Vybrid Processors</title>
    <link>https://community.nxp.com/t5/Vybrid-Processors/Binary-Loading-TCM-and-OCRAM/m-p/327584#M3168</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In Vybrid Architecture manual, a TCM backdoor is intended to load the code and data into TCM by Cortex-A5 (primary core) prior to running Cortex-M4 (secondary core).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It actual it is loaded in the OCRAM-SysRAM0.&amp;nbsp; Can anybody explain why it is loaded in SysRAM0 and not in the TCM?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 05 Dec 2014 09:50:08 GMT</pubDate>
    <dc:creator>carlovalgocela</dc:creator>
    <dc:date>2014-12-05T09:50:08Z</dc:date>
    <item>
      <title>Binary Loading : TCM and OCRAM</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Binary-Loading-TCM-and-OCRAM/m-p/327584#M3168</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In Vybrid Architecture manual, a TCM backdoor is intended to load the code and data into TCM by Cortex-A5 (primary core) prior to running Cortex-M4 (secondary core).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It actual it is loaded in the OCRAM-SysRAM0.&amp;nbsp; Can anybody explain why it is loaded in SysRAM0 and not in the TCM?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 05 Dec 2014 09:50:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Binary-Loading-TCM-and-OCRAM/m-p/327584#M3168</guid>
      <dc:creator>carlovalgocela</dc:creator>
      <dc:date>2014-12-05T09:50:08Z</dc:date>
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    <item>
      <title>Re: Binary Loading : TCM and OCRAM</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Binary-Loading-TCM-and-OCRAM/m-p/327585#M3169</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Carlo,&lt;/P&gt;&lt;P&gt;missing some information like which code or data, what project...&lt;/P&gt;&lt;P&gt;Anyway, generally the placement of the code and data depends on Linker command file (IAR) - see &lt;CITE class="_Rm"&gt;supp.&lt;STRONG&gt;iar&lt;/STRONG&gt;.com&lt;/CITE&gt;&lt;CITE class="_Rm"&gt; &lt;/CITE&gt;or scatter file&amp;nbsp; (DS5) - see &lt;A href="http://infocenter.arm.com/" title="http://infocenter.arm.com/"&gt;Loading this site&lt;/A&gt;&lt;/P&gt;&lt;P&gt;Depending on your IDE you can select location of your code and date and build the project with this setting. Then your code will be placed where you want.&lt;/P&gt;&lt;P&gt;/Jiri&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 10 Dec 2014 16:11:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Binary-Loading-TCM-and-OCRAM/m-p/327585#M3169</guid>
      <dc:creator>jiri-b36968</dc:creator>
      <dc:date>2014-12-10T16:11:19Z</dc:date>
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    <item>
      <title>This an automatic process.  We are marking this post as s...</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Binary-Loading-TCM-and-OCRAM/m-p/1135601#M6042</link>
      <description>&lt;B&gt;This an automatic process.&lt;/B&gt;&lt;BR /&gt;&lt;BR /&gt;
We are marking this post as solved, due to the either low activity or any reply marked as correct.&lt;BR /&gt;&lt;BR /&gt;
If you have additional questions, please create a new post and reference to this closed post.&lt;BR /&gt;&lt;BR /&gt;
NXP Community!</description>
      <pubDate>Thu, 03 Sep 2020 14:39:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Binary-Loading-TCM-and-OCRAM/m-p/1135601#M6042</guid>
      <dc:creator>CommunityBot</dc:creator>
      <dc:date>2020-09-03T14:39:32Z</dc:date>
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