topic Re: Performance problem A5 processor in Vybrid Processors

Performance problem A5 processor

x_dex — Tue, 22 Apr 2014 09:33:27 GMT

I am running an existing performance test code with the A5 processor of TWR-VF65GS10 development tower. To debug the program I use a DS-5 compiler, the processor is set to 480MHz. But the measured performance test time is too high, the previous used 120MHz processor runs the test code in 0,2s the A5 needs 2s.

Is there any possible processor setting, slowing down the A5 performance?

I run the program in debug mode with DS-5 tool over SDA interface, is it possible this slows down the A5 performance?

Re: Performance problem A5 processor

jiri-b36968 — Tue, 29 Apr 2014 06:28:36 GMT

Hello Juergen,

No OpenSDA is not slowing down the CA5 core. OpenSDA itself is not the fastest (runs only on 1MHz), but once command to RUN is executed it has no influence on the CA5 core.

Speed of CA5 computing depends on many factors. For example:

for mathematics operation if floating point if VFP is enabled
speed of the core
MMU setting / cache enable (L1 D, L1 C, L2)
source code location
...

/Jiri

Re: Performance problem A5 processor

x_dex — Tue, 29 Apr 2014 16:44:37 GMT

I’m using a DS-5 compiler to debug a TWR-VF65GS10 development tower with processor speed of 480MHz.

Which setting should the MMU have to get a max performance?

In which registers can I check the MMU / cache settings of the processor?

How can I enable VFP?

Re: Performance problem A5 processor

jiri-b36968 — Wed, 30 Apr 2014 08:28:31 GMT

Hello Juergen,

1. VFP can be enabled using Cortex A5 registers:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0449b/ch02s01s02.html

I used

asm ( "MRC p15, 0, r0, c1, c1, 2");

asm ( "ORR r0, r0, #0xC00" );

asm ( "MCR p15, 0, r0, c1, c1, 2");

asm ( "MOV r0, #0x03c00000");

asm ( "MCR p15, 0, r0, c1, c0, 2");

asm ( "MOV r3, #0x40000000");

asm ( "VMSR FPEXC, r3");

please note that compiler has to be set to use VFP instructions

2. similar for MMU. Need to set MMU translation tables, regions, enable caches (L1,L2) There is lot of information on infocenter.ar.com. But you can reuse code which is part of MQX.

0. But first of all please describe your application. What you want to achieve?

/Jiri

Re: Performance problem A5 processor

amarti — Wed, 09 Jul 2014 07:20:49 GMT

Hello Jiri

I'm working on the same issue as Juergen. We assume that there are no explicit cache, mmu, fpu settings in Freescale's vybird sample code.

Unfortunately I'm not very familiar with cache / MMU setup resp. can not implement the general instructions provided by ARM's documentation.

Could you provide me some hints / examples, where and how I should make these setups?

Andi

Re: Re: Performance problem A5 processor

jiri-b36968 — Mon, 04 Aug 2014 09:34:11 GMT

Hi Andreas,

I would recommend you to utilize MQX code:

You need to reuse files with cache.c, cache_a5.c etc. (old versions attached)

and you need to define MMU TLBs for example like this:

// turn on MMU - create table, fill 4k items, change necessery ones items

void cache_setting_a5(void) {

#ifdef MMU_TLB

// available cahce setting:

// PSP_PAGE_TYPE_CACHE_WTNWA,

// PSP_PAGE_TYPE_CACHE_WBNWA,

// PSP_PAGE_TYPE_CACHE_NON,

/* Enable MMU and L1 cache */

/* alloc L1 mmu table */

//L1PageTable = _mem_alloc_align(MMU_TRANSLATION_TABLE_SIZE, MMU_TRANSLATION_TABLE_ALIGN);

/* None cacheable is comon with strongly ordered. MMU doesnt work with another init configuration */

_mmu_vinit(PSP_PAGE_TABLE_SECTION_SIZE(PSP_PAGE_TABLE_SECTION_SIZE_1MB) | PSP_PAGE_DESCR(PSP_PAGE_DESCR_ACCESS_RW_ALL) | PSP_PAGE_TYPE(PSP_PAGE_TYPE_STRONG_ORDER), (pointer)L1PageTable);

/* add region in sram area */

_mmu_add_vregion((pointer)__INTERNAL_SRAM_BASE, (pointer)__INTERNAL_SRAM_BASE, (_mem_size) 0x00100000, PSP_PAGE_TABLE_SECTION_SIZE(PSP_PAGE_TABLE_SECTION_SIZE_1MB) | PSP_PAGE_TYPE(PSP_PAGE_TYPE_CACHE_WBNWA) | PSP_PAGE_DESCR(PSP_PAGE_DESCR_ACCESS_RW_ALL));

/* add cached region in ddr area */

// !!!!! SDRAM not working when GRAM + QSPIO + GSPI1 TLB enabled !!!!!

_mmu_add_vregion((pointer)__EXTERNAL_DDRAM_BASE, (pointer)__EXTERNAL_DDRAM_BASE, __EXTERNAL_DDRAM_SIZE, PSP_PAGE_TABLE_SECTION_SIZE(PSP_PAGE_TABLE_SECTION_SIZE_1MB) | PSP_PAGE_TYPE(PSP_PAGE_TYPE_CACHE_WBNWA) | PSP_PAGE_DESCR(PSP_PAGE_DESCR_ACCESS_RW_ALL));

/* add cached region in gram area */

//_mmu_add_vregion((pointer)__INTERNAL_GRAM_BASE, (pointer)__INTERNAL_GRAM_BASE, __INTERNAL_GRAM_SIZE, PSP_PAGE_TABLE_SECTION_SIZE(PSP_PAGE_TABLE_SECTION_SIZE_1MB) | PSP_PAGE_TYPE(PSP_PAGE_TYPE_CACHE_WBNWA) | PSP_PAGE_DESCR(PSP_PAGE_DESCR_ACCESS_RW_ALL));

/* add cached region in QSPI0 area */

//_mmu_add_vregion((pointer)__EXTERNAL_QSPI0_BASE, (pointer)__EXTERNAL_QSPI0_BASE, __EXTERNAL_QSPI0_SIZE, PSP_PAGE_TABLE_SECTION_SIZE(PSP_PAGE_TABLE_SECTION_SIZE_1MB) | PSP_PAGE_TYPE(PSP_PAGE_TYPE_CACHE_WBNWA) | PSP_PAGE_DESCR(PSP_PAGE_DESCR_ACCESS_RW_ALL));

/* add cached region in QSPI1 area */

//_mmu_add_vregion((pointer)__EXTERNAL_QSPI1_BASE, (pointer)__EXTERNAL_QSPI1_BASE, __EXTERNAL_QSPI1_SIZE, PSP_PAGE_TABLE_SECTION_SIZE(PSP_PAGE_TABLE_SECTION_SIZE_1MB) | PSP_PAGE_TYPE(PSP_PAGE_TYPE_CACHE_WBNWA) | PSP_PAGE_DESCR(PSP_PAGE_DESCR_ACCESS_RW_ALL));

_mmu_venable();

#endif

_dcache_enable();

_icache_enable();

}

/Jiri