topic Re: about a logic of PFD in Vybrid Processors

about a logic of PFD

soichiyamamoto — Fri, 09 May 2014 12:47:59 GMT

Hi,

My customer have question about the logic of the divider circuit of PFD.

A circuit of PFD is not a simple divider circuit from the following expression.

PFDn Output Frequency = PLLx Output Frequency * (18/PFDn_FRAC)

Q1)Please tell me about a logic of PFD in detail.

Best Regards,

soichi

Re: about a logic of PFD

naoumgitnik — Fri, 09 May 2014 22:20:46 GMT

Dear Soichi,

May I ask what triggered this question, please?

If something is not working for your customer, may you be more specific?
If you are simply asking about the theory of PFD operation, then it is in the general theory of Fractional PLL operation. Of course, each company applies this theory in its own manner, with their own tricks, but I am afraid they are considered confidential.

Regards, Naoum Gitnik.

Re: Re: about a logic of PFD

soichiyamamoto — Fri, 09 May 2014 23:25:02 GMT

Dear Naoum,

Thank you for fast reply.

The reason is because my customer had the following question.

・Does the output clock become the wave pattern of the duty ratio in PFD_FRAC = 35 and PFD_FRAC = 34?

・When the frequency is not divisible in the logic of the divider, what kind of wave pattern does it become?

Best Regards,

soichi

Re: about a logic of PFD

naoumgitnik — Fri, 09 May 2014 23:33:38 GMT

Dear Soichi

>> Does the output clock become the wave pattern of the duty ratio in PFD_FRAC = 35 and PFD_FRAC = 34?

Sorry, I am having difficulties understanding the question - may you provide more details / examples, please?

>> When the frequency is not divisible in the logic of the divider, what kind of wave pattern does it become?

I guess you mean what to do when the required exact frequency cannot be reached by division/multiplication? - The only solution in this case is to get to the actual frequency as close as possible to the required one and verify if this actual frequency value is within the allowed tolerance for the required frequency value.

Sincerely, Naoum Gitnik.

Re: about a logic of PFD

soichiyamamoto — Fri, 09 May 2014 23:48:42 GMT

Dear Naoum,

>> Does the output clock become the wave pattern of the duty ratio in PFD_FRAC = 35 and PFD_FRAC = 34?
Sorry, I am having difficulties understanding the question - may you provide more details / examples, please?

PFD_FRAC = 35 and PFD_FRAC = 34 , Do both become the wave pattern of the 50%duty ratio?

>> When the frequency is not divisible in the logic of the divider, what kind of wave pattern does it become?
I guess you mean what to do when the required exact frequency cannot be reached by division/multiplication? - The only solution in this case is to get to the actual frequency as close as possible to the required one and verify if this actual frequency value is within the allowed tolerance for the required frequency value.

Yes,

When the required exact frequency cannot be reached by division/multiplication, Does a normal wave pattern output PFD? Or does a malformed wave pattern output it?

Best regards,

soichi

Re: Re: about a logic of PFD

soichiyamamoto — Sun, 11 May 2014 11:28:40 GMT

Dear Naoum,

I ask you a question by addition.

Please tell me about PLL2.

Q1）

Please tell me the Minimum frequency that I can output in PFD.

Q2）

In the case of PLL=480MHz, PFD = 35, PFD OUT is 246MHz.

Does the amplitude of the wave pattern become small when it becomes the frequency that is lower than 246MHz?

Q3)

Please give me a characteristic of PLL2 VCO.

Best regards,

soichi

Re: about a logic of PFD

naoumgitnik — Mon, 12 May 2014 22:02:23 GMT

Dear Soichi,

I see now that your concern is the waveform quality. - No, what is defined by PFD is frequency, and the shape (amplitude, duty cycle) should be as stated in our documentation.
Please, refer to the Reference Manual for the PLL2 details.

May I ask you what triggered such questions, please?

Has the customer observed any specific issues in their design? - It would be much more efficient to focus on specific issues instead of discussing general operation of the PLLs.

Regards, Naoum Gitnik.

Re: about a logic of PFD

soichiyamamoto — Mon, 12 May 2014 23:28:35 GMT

Dear Naoum,

Thank you.

May I ask you what triggered such questions, please?

My customer use CRYSTAL RESONATOR.

However, there is not it just at 24MHz.

How much error is permitted?

Is it +-10%?

My customer worry about it.

This is the intention of this question.

Best regards,

Soichi

Re: about a logic of PFD

soichiyamamoto — Mon, 12 May 2014 23:32:11 GMT

Dear Naoum,

Please give me an answer about the following question.

Soichi Yamamoto<https://community.freescale.com/people/soichiyamamoto> 2014/05/12 14:06 (Soichi Yamamoto への返信<https://community.freescale.com/message/402543?et=watches.email.thread#402145>)

I ask you a question by addition.

Please tell me about PLL2.

Q1）

Please tell me the Minimum frequency that I can output in PFD.

Q2）

In the case of PLL=480MHz, PFD = 35, PFD OUT is 246MHz.

Does the amplitude of the wave pattern become small when it becomes the frequency that is lower than 246MHz?

Q3)

Please give me a characteristic of PLL2 VCO.

Best regards,

soichi

Re: about a logic of PFD

naoumgitnik — Tue, 13 May 2014 21:07:42 GMT

Dear Soichi,

Please, find my answers below.

>> PFD_FRAC = 35 and PFD_FRAC = 34 , Do both become the wave pattern of the 50% duty ratio?

- The duty cycle values for various PLLs, for the entire frequency range (i.e. for all the PFD_FRAC values) are provided in the Datasheet, Tables 68 to 72.

>> When the required exact frequency cannot be reached by division/multiplication, Does a normal wave pattern output PFD? Or does a malformed wave pattern output it?

>> In the case of PLL=480MHz, PFD = 35, PFD OUT is 246MHz. Does the PLL2 amplitude of the wave pattern become small when it becomes the frequency that is lower than 246MHz?

- No, the waveform is not distorted (including its amplitude) at any frequency in the range described in our documentation.

>> Please give me a characteristic of PLL2 VCO.

- Details of the internal product structure are considered confidential.

>> My customer uses CRYSTAL RESONATOR. However, there is not it just at 24MHz. How much error is permitted? Is it +-10%?

- We assume in our documentation that it is 24MHz. Of course, deviation from this value is inevitable, but it is tens of PPM, not %. Theoretically, the device can use a wider frequency range but:

1. It will have a serious impact "down the road”, i.e. for the blocks using this frequency as a source,

2. Device operation only in the conditions described in the Datasheet is supported.

(BTW, it is hard to imagine a condition in which it is impossible to generate the required frequency with the high fractional "granularity” the device offers…)

>> Please tell me the Minimum frequency that I can output in PFD.

May you be more specific, please? What is the customer's goal? What frequency would you like to have on the output?

Regards, Naoum Gitnik.

Re: about a logic of PFD

soichiyamamoto — Wed, 14 May 2014 01:09:25 GMT

Dear Naoum,

Thank you for reply.

>> Please tell me the Minimum frequency that I can output in PFD.
May you be more specific, please? What is the customer's goal? What frequency would you like to have on the output?

In the case of PLL2=480MHz PFD_FRAC = 35,

Is the Minimum frequency of PFD 246857142.9Hz?

Best Regards,

Soichi

Re: Re: about a logic of PFD

shigenobukatagi — Wed, 14 May 2014 04:19:31 GMT

Hi Naoum,

Let me share the background of this question.

The customer's board still has a issue that DDRMC doesn't finish the initialization after recovering from LPSTOP3 mode.

After the debugging, they found that DDRMC's source PLL2 PFD2 output may have a problem. This phenomena disappears if PFD_FRAC is changed from 34 to 35. 35 is the upper limit, so their concern is the lower limit of PLL PFD2 output frequency.

If PLL2 specification has no issue for this use case as you mentioned, we need to find other way to debug it.

We asked customer to input clean 24MHz clock instead of crystal again, but current board is too small to do that.

Could you please advise us how we can figure out the root cause?

I think monitoring 24MHz source clock through CLKO pin is one of ways, I would appreciate if you share better way.

Best Regards,

Shigenobu

Re: about a logic of PFD

naoumgitnik — Wed, 14 May 2014 16:45:25 GMT

Dear Soichi,

You are using settings from our Reference Manual, right? They have been tested during the product verification, and if the value you provided is calculated based on this, than this is it (I am sorry but I can only repeat this calculation after you if it makes sense… unless I am missing something here…).

BTW, how do we know the problem is on the Vybrid, not the DDR side? E.g. frequencies, timing, etc. for the DDR chip.

Regards, Naoum Gitnik.

Re: about a logic of PFD

naoumgitnik — Wed, 14 May 2014 17:11:28 GMT

Dear shigenobukatagiri-b39676,

Thanks for your help in this thread!

I "brain-stormed" this issue with my colleagues (Richard Stulens and Ross McLuckie, thank you!) , and below is our "joint" reply:

You are the author of the "LPStop entry/exit with DDR3 data retention" code successfully tested on our Vybrid Tower board, right?

· IMO, if the customer is using your code but having issues, we have to focus on the differences between our and their designs - components used, schematic differences, maybe layout (much less likely...), etc.

Maybe there is significant jitter on the DDRC clock (due to specific layout).
It looks like the i.MX6 product has a PDF issue (do not know all the details), and the workaround for it (not necessarily applicable here, BTW) is to reset the PFD first before enabling the DDR Controller.
The workaround by setting different PFD settings could point to marginal design; due to that, the customer needs to check if they are not violating any DDR chip's spec, e.g. minimum frequency, stabilization time, etc.
It is possible to wake up with a temporary frequency value, and then switch to the required, permanent, one.
If the customer is using LPDDR2 - we only tested DDR3 (thanks to Shigenobu Katagiri!).

Regards, Naoum Gitnik.

(soichiyamamoto)

Re: Re: about a logic of PFD

shigenobukatagi — Thu, 15 May 2014 07:52:54 GMT

Hi Naoum, (also Richard and Ross)

Thank you for your help. we have update, so let me summarize it again.

Customer's issue :

Occasionally customer's system fails to recover from LPSTOPx mode.

DDRMC cannot finish its initialization because PLL2 PFD2 doesn't oscillate.

They has confirmed that 24MHz crystal oscillated when this issue happened, so PLL should be something wrong.

24MHz oscillation could be observed through CKO1 pin.

Here's the summary. Find details latter half why I made them.

1. Need FSL internal review for the sample code. -> FSL

2. Waveform measurement for both 24MHz and PLL PFD2 output, mainly for the jitter. -> Soich-san will report here

3. Confirm the margin based on the specification of LPDDR2 chip which customer uses -> Soich-san

Bolds are my reply for you:

You are the author of the "LPStop entry/exit with DDR3 data retention" code successfully tested on our Vybrid Tower board, right?

It's very low error rate on customer's side, so I cannot say that my sample code doesn't have same issue.

We need internal discussion for this.

Maybe there is significant jitter on the DDRC clock (due to specific layout).

Soichi-san is working on measuring it.

Seems accuracy of 24MHz frequency might have problem.

It looks like the i.MX6 product has a PDF issue (do not know all the details), and the workaround for it (not necessarily applicable here, BTW) is to reset the PFD first before enabling the DDR Controller.

This was a kind of initialization issue, my sample code should be reviewed internally to avoid similar issue.

The workaround by setting different PFD settings could point to marginal design; due to that, the customer needs to check if they are not violating any DDR chip's spec, e.g. minimum frequency, stabilization time, etc.

Soichi-san is working on this.

It is possible to wake up with a temporary frequency value, and then switch to the required, permanent, one.

In my opinion, changing PFD divide value from 35 to 34 is just a situation. it's hard to be a workaround unless any reasonable explanation.

If the customer is using LPDDR2 - we only tested DDR3 (thanks to Shigenobu Katagiri!).

According to the investigation, this issue is not related to the type of memory since the probrem isPLL PFD2

Best Regards,

Shigenobu

Re: about a logic of PFD

naoumgitnik — Thu, 15 May 2014 16:32:35 GMT

Thanks Shigenobu!

Please, keep me in the loop.

Regards, Naoum Gitnik.

Re: Re: about a logic of PFD

shigenobukatagi — Fri, 16 May 2014 00:39:12 GMT

Hi Soichi-san,

FSL AE team has reviewed PLL initialization part in sample code, found one concern.

Here's the comment from them.

----------------------------------------------------------------------------------------------------------------------------------------------

I wonder if maybe the PFD is affected by clock jitter from the PLL when it starts up. We have seen some problems on i.MX6 with enabling the PFD before the PLL was locked.

You can try to leave the PLL in bypass mode and the PFD disabled (PFDx_CLKGATE) until the PLL is locked (wait for LOCK bit in PLLx_CTRL)

Then remove bypass and enable PFD.

----------------------------------------------------------------------------------------------------------------------------------------------

Could you please ask customer to implement it?

We can also provide revised sample code locally.

Best Regards,

Shigenobu

Re: about a logic of PFD

karina_valencia — Fri, 23 May 2014 22:13:15 GMT

shigenobukatagiri-b39676 can you review and answer previous comments from Naoum?