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    <title>topic Re: Vybrid core clock setting in Vybrid Processors</title>
    <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-core-clock-setting/m-p/292466#M2355</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thank you Bill, you solve my problem. &lt;/P&gt;&lt;P&gt;The clock is initialised in &lt;STRONG class="final-path"&gt;lowlevel_init.S &lt;/STRONG&gt;file in u-boot source. &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 25 Nov 2013 11:22:51 GMT</pubDate>
    <dc:creator>jeremyesquirol</dc:creator>
    <dc:date>2013-11-25T11:22:51Z</dc:date>
    <item>
      <title>Vybrid core clock setting</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-core-clock-setting/m-p/292464#M2353</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi !&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm using a TWR-VF6xx with Embedded Linux on cortex-A5 core. It seems that the core clock is set to 396Mhz using &lt;STRONG&gt;PLL1_PFD3&lt;/STRONG&gt; (register value read with DS-5).&lt;/P&gt;&lt;P&gt;First, I don't understand where the core clock is initialized ? I've seen in file &lt;STRONG&gt;clock.c &lt;/STRONG&gt;that all clocks are registered but the function :&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;PRE __default_attr="c++" __jive_macro_name="code" class="jive_text_macro jive_macro_code _jivemacro_uid_13850494724606937" jivemacro_uid="_13850494724606937"&gt;
&lt;P&gt;int&amp;nbsp; __init mvf_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2)&lt;/P&gt;
&lt;P&gt;[...]&lt;/P&gt;
&lt;P&gt;// keep correct count&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; cpu_clk.usecount++;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; pll1_sys_main_clk.usecount += 5;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; pll2_528_bus_main_clk.usecount += 5;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; periph_clk.usecount++;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ipg_clk.usecount++;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;#if 0&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; clk_set_parent(&amp;amp;periph_clk, &amp;amp;pll2_pfd2_396M);&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; clk_enable(&amp;amp;periph_clk); /* platform bus clk */&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; clk_enable(&amp;amp;ipg_clk); /* ips bus clk */&lt;/P&gt;
&lt;P&gt;#endif&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; clk_enable(&amp;amp;pll3_usb_otg_main_clk);&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;

&lt;/PRE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;only enable pll3_usb_otg_main_clock ? Where are enabled the others?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Second, there are some vybrid specific function in this file, and my goal is just to set the core clock to 450Mhz. I just modify the &lt;STRONG&gt;.parent&lt;/STRONG&gt; of the &lt;STRONG&gt;PLL1_SW_CLK &lt;/STRONG&gt;by&lt;STRONG&gt; PLL1_PFD2_450M&lt;/STRONG&gt; using the function&lt;/P&gt;&lt;PRE __default_attr="c++" __jive_macro_name="code" class="jive_text_macro jive_macro_code _jivemacro_uid_13850494724434724" jivemacro_uid="_13850494724434724"&gt;
&lt;P&gt;static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)&lt;/P&gt;

&lt;/PRE&gt;&lt;P&gt;but it seems that has no effect. &lt;SPAN class="short_text" lang="en"&gt;&lt;SPAN class="hps"&gt;Is&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;anyone&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;can help me?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 21 Nov 2013 15:56:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-core-clock-setting/m-p/292464#M2353</guid>
      <dc:creator>jeremyesquirol</dc:creator>
      <dc:date>2013-11-21T15:56:03Z</dc:date>
    </item>
    <item>
      <title>Re: Vybrid core clock setting</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-core-clock-setting/m-p/292465#M2354</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Some clocks are assumed to be initialized by the boot loader (u-boot).&amp;nbsp; U-boot must also initialize many of these clocks to work with the 'fec' and to load your Linux kernel.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If you are restarting the core clock, you may need to re-initialize some things and probably can not have SDRAM, etc running as those clock modules will be derived from the main PLL; at least this is the case with other Freescale CPUs.&amp;nbsp; You are probably better off looking at the u-boot source, if you don't want to do this dynamically.&amp;nbsp; The source is at &lt;A href="https://github.com/Timesys/u-boot-timesys.git" title="https://github.com/Timesys/u-boot-timesys.git"&gt;Timesys/u-boot-timesys · GitHub&lt;/A&gt;.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 21 Nov 2013 21:17:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-core-clock-setting/m-p/292465#M2354</guid>
      <dc:creator>billpringlemeir</dc:creator>
      <dc:date>2013-11-21T21:17:26Z</dc:date>
    </item>
    <item>
      <title>Re: Vybrid core clock setting</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-core-clock-setting/m-p/292466#M2355</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thank you Bill, you solve my problem. &lt;/P&gt;&lt;P&gt;The clock is initialised in &lt;STRONG class="final-path"&gt;lowlevel_init.S &lt;/STRONG&gt;file in u-boot source. &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 25 Nov 2013 11:22:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-core-clock-setting/m-p/292466#M2355</guid>
      <dc:creator>jeremyesquirol</dc:creator>
      <dc:date>2013-11-25T11:22:51Z</dc:date>
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