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    <title>topic Re: Vybrid DMA inter-core collisions in Vybrid Processors</title>
    <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-DMA-inter-core-collisions/m-p/284833#M2073</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Petr,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt; On the Vybrid Tower board, Linux uses the following DMA channels on DMA engine 0, mux 0:&lt;BR /&gt; &lt;BR /&gt; UART1 RX - Channel 4&lt;BR /&gt; UART1 TX - Channel 5&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;DSPI0 RX - Channel 12&lt;/P&gt;&lt;P&gt;DSPI0 TX - Channel 13&lt;/P&gt;&lt;P&gt;&lt;BR /&gt; SAI2 (I2S2) RX - Channel 20&lt;BR /&gt; SAI2 (I2S2) TX - Channel 21&lt;BR /&gt; &lt;BR /&gt;A list of all DMA channels can be found in the Linux source tree, at arch/arm/plat-mxc/include/mach/mvf_edma.h&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks, and let me know if you have any questions.&lt;BR /&gt; &lt;BR /&gt;Timesys Support&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 10 Mar 2014 20:33:23 GMT</pubDate>
    <dc:creator>timesyssupport</dc:creator>
    <dc:date>2014-03-10T20:33:23Z</dc:date>
    <item>
      <title>Vybrid DMA inter-core collisions</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-DMA-inter-core-collisions/m-p/284831#M2071</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Two months ago, I described a DMA collision issue with Vybrid audio when a playback is started on Linux (A5) while MQX is running on M4 (&lt;A href="https://community.nxp.com/thread/317985"&gt;Vybrid audio (sgtl5000)&lt;/A&gt;).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Now I am experiencing a mirror problem - when an SPI DMA operation starts on M4, Linux immediately dies. Is there any document describing which DMA channels are used by Timesys Linux so I can setup MQX to use different channels and avoid the issues? Can that be easily seen/modified in the Linux sources?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Mar 2014 06:52:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-DMA-inter-core-collisions/m-p/284831#M2071</guid>
      <dc:creator>kubiznak_petr</dc:creator>
      <dc:date>2014-03-10T06:52:28Z</dc:date>
    </item>
    <item>
      <title>Re: Vybrid DMA inter-core collisions</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-DMA-inter-core-collisions/m-p/284832#M2072</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/timesyssupport"&gt;timesyssupport&lt;/A&gt; can you attend this case?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Mar 2014 19:17:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-DMA-inter-core-collisions/m-p/284832#M2072</guid>
      <dc:creator>karina_valencia</dc:creator>
      <dc:date>2014-03-10T19:17:03Z</dc:date>
    </item>
    <item>
      <title>Re: Vybrid DMA inter-core collisions</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-DMA-inter-core-collisions/m-p/284833#M2073</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Petr,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt; On the Vybrid Tower board, Linux uses the following DMA channels on DMA engine 0, mux 0:&lt;BR /&gt; &lt;BR /&gt; UART1 RX - Channel 4&lt;BR /&gt; UART1 TX - Channel 5&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;DSPI0 RX - Channel 12&lt;/P&gt;&lt;P&gt;DSPI0 TX - Channel 13&lt;/P&gt;&lt;P&gt;&lt;BR /&gt; SAI2 (I2S2) RX - Channel 20&lt;BR /&gt; SAI2 (I2S2) TX - Channel 21&lt;BR /&gt; &lt;BR /&gt;A list of all DMA channels can be found in the Linux source tree, at arch/arm/plat-mxc/include/mach/mvf_edma.h&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks, and let me know if you have any questions.&lt;BR /&gt; &lt;BR /&gt;Timesys Support&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Mar 2014 20:33:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-DMA-inter-core-collisions/m-p/284833#M2073</guid>
      <dc:creator>timesyssupport</dc:creator>
      <dc:date>2014-03-10T20:33:23Z</dc:date>
    </item>
    <item>
      <title>Re: Vybrid DMA inter-core collisions</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-DMA-inter-core-collisions/m-p/284834#M2074</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Good, that should help, thank you.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Mar 2014 17:19:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-DMA-inter-core-collisions/m-p/284834#M2074</guid>
      <dc:creator>kubiznak_petr</dc:creator>
      <dc:date>2014-03-11T17:19:07Z</dc:date>
    </item>
    <item>
      <title>Re: Vybrid DMA inter-core collisions</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-DMA-inter-core-collisions/m-p/284835#M2075</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/timesyssupport"&gt;timesyssupport&lt;/A&gt;​&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;i would like to ask how in Linux the peripherals are assigned to DMA channels on DMA engine 0, mux 0?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 10 Jun 2015 00:48:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-DMA-inter-core-collisions/m-p/284835#M2075</guid>
      <dc:creator>carlovalgocela</dc:creator>
      <dc:date>2015-06-10T00:48:21Z</dc:date>
    </item>
    <item>
      <title>Re: Vybrid DMA inter-core collisions</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-DMA-inter-core-collisions/m-p/284836#M2076</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/carlovalgocela"&gt;carlovalgocela&lt;/A&gt;​&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The following link should be helpful:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://linuxlink.timesys.com/docs/wiki/engineering/bsp_userguide_twr-vf65gs10#DMA"&gt;https://linuxlink.timesys.com/docs/wiki/engineering/bsp_userguide_twr-vf65gs10#DMA&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you,&lt;/P&gt;&lt;P&gt;Timesys Support&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 11 Jun 2015 15:43:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-DMA-inter-core-collisions/m-p/284836#M2076</guid>
      <dc:creator>timesyssupport</dc:creator>
      <dc:date>2015-06-11T15:43:36Z</dc:date>
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