topic Re: Exploring Vybrid A5 QSPI XIP performance in Vybrid Processors

Exploring Vybrid A5 QSPI XIP performance

nancyb — Wed, 05 Feb 2014 18:43:03 GMT

I am exploring the Execution In Place (XIP) performance for an MQX application running on the Vybrid A5 core on a TWR-VF65GS10 board using the on-board QSPI memory. My test application utilizes the MQX shell, MFS, and SD card resources. I also have some custom code that allows me to access the MQX QSPI interface when the application runs out of SRAM. I discovered that MQX won't initialize the QSPI driver when executing out of QSPI; a restriction that makes sense but I wanted try it anyway.

Development in IAR 6.70 and using the quadspi_loader project in the Vybrid Sample Code to take the binary and flash it into the QuadSPI on the TWR-VF65GS10.

For my initial successful XIP build and boot I used quadspi_boot.c and a modified linker command file from the Vybrid Sample Code. The QSPI ran in SDR Single mode with the clock default in quadspi_boot.c set to 1. According to the Vybrid Reference Manual, page 902, this corresponds to an 18 MHz clock. I used a directory command to a subfolder on the SD card for a crude benchmark. Running from QSPI the "dir" command executed in about 2 seconds. In comparison, when running from SRAM the same command completed in about 85 ms.

In another thread, Re: MQX application is not booting from QuadSPI_NAND flash, I found a boot configuration that ran in SDR Quad mode. I updated and reran my benchmark and the "dir" command executed in about 750 ms; a noticeable improvement. A setting in quadspi_conf indicated that a clock setting of 1 is 60 MHz.

1, /* SCLK Freq - 60Mhz*/

Next I tried to improve the XIP performance. I increased SCLK frequency to 74 MHz and 99 MHz but neither configuration would boot. I also tried to set up quadspi to run in DDR mode without success by modifying the LUT to use DDR quad mode:

0x04ED, // CMD DDRQIOR

0x2A18, // ADDR_DDR (4) 24

0x0C08, // DUMMY 8

0x3280, // READ_DDR (4) 0x80

0x2400, // JMP_CS 0

I am still coming up to speed with QSPI so I wasn't surprised that my LUT sequence did not work.

I stepped through MQX startup and observed the I-cache being enabled. I plan to do some experiments to determine how using I-cache affects performance.

Questions:

1. Can the SCLK frequency be increased? Is more needed than changing the quadspi_conf value? I stepped through MQX changing QSPI clock speed and the experience was character building.

2. Has anyone configured QSPI XIP with higher clock speed or DDR?

3. Are there any cache adjustments that would boost XIP performance?

Re: Exploring Vybrid A5 QSPI XIP performance

erickcastillo — Sat, 01 Mar 2014 18:28:17 GMT

Hi Nancy,

Any chance you've succeeded in this effort to execute in place over QSPI running in DDR mode? I am going through this process now on my tower board and have run into the same issue.

The LUT sequence I am using is the following:

// SEQID 0 - Quad DDR Read (For DDR, Quad I/O Mode)

// -----------------------------------------------------------------------------------

0x04ED, = CMD | 1 Pad | DDRQIOR

0x2A18, = ADDR_DDR | 4 Pads | 24 bits will be used.

0x2EA5, = MODE_DDR | 4 Pads | Notifies of re-issuing read at the end of access.

0x0E06, = DUMMY | 4 Pads | 6 Cycles

0x3A80, = READ_DDR | 4 Pads | Read 128 bits

0x2401, = JMP_ON_CS | NA | Go to ADDR_DDR

This differs from your sequence in 3 ways.

1. I am trying to enable continuous read mode by sending the MODE_DDR command and setting the JMP_ON_CS command accordingly.

2. The READ_DDR command is set differently from your sequence (perhaps a typo?).

3. I specify 6 Dummy cycles (per the Latency Codes table 8.11 of the Spansion data sheet).

I took this block from the vybrid_sc sample code which shows a bunch of LUT sample entries so I assume it should work.

At the moment, my suspicion is that I do not have the sampling point (at offset 61 of the configuration table) set correctly; I'm going to sweep through the 7 possible values of this entry and cross my fingers that one of them works.

Other settings from the configuration table:

//TYPO: Serial Clock Frequency: 00 -> 60 Mhz

//Correction: Serial Clock Frequency: 01 -> 60MHz@

Mode of operation: 04 -> Quad Mode

DDR Enable: 1 -> DDR Enabled

Please let me know if you've figured this one out!

Thanks,

--Erick

Re: Exploring Vybrid A5 QSPI XIP performance

naoumgitnik — Mon, 03 Mar 2014 21:40:31 GMT

Dear nancyb,

To make it really visible, I would recommend you to move the thread from your personal space to the "Vybrid Processors" one.

Sincerely, Naoum Gitnik.

(erickcastillo)

Re: Exploring Vybrid A5 QSPI XIP performance

nancyb — Tue, 04 Mar 2014 12:38:18 GMT

Hi Naoum,

Is there a process to move the thread to Vybrid or should I just create a new topic and cut/paste my original entry? It would be useful to have Erick's reply too.

Nancy

Re: Exploring Vybrid A5 QSPI XIP performance

nancyb — Tue, 04 Mar 2014 12:51:07 GMT

Hi Erick,

I have not worked this issue recently. After receiving excellent help setting up the I cache my XIP (execute in place) performance is better than SRAM. I will be coming back to this topic because our application will need the best XIP performance I can achieve. You indicate that

Serial Clock Frequency: 00 -> 60 Mhz

and the Vybrid Reference Manual, Rev 5, 07/2013 on page 842 shows

Value Clock

00 18 MHz

01 60 MHz

02 74 MHz

03 99Mhz (only SDR mode)

In any case no value except 1 worked for me, perhaps because I did not tweak the sampling point.

Nancy

Re: Exploring Vybrid A5 QSPI XIP performance

naoumgitnik — Tue, 04 Mar 2014 18:33:10 GMT

Dear Nancy,

It is quite simple to move - you open this thread, and as its author, you see a "Move" option among the "ACTIONS" on the right (select the "Vybrid Processors" space).
I already replied to the Freescale FAE for Eric, and, unfortunately, in the internal Freescale space - it contains some information from the new Vybrid Datasheet, which will be published only in a few weeks. If you need this information urgently, you will also have to turn to our FAE - they all have access to it. The point here is that we are making our documentation, specifically in the QSPI part, clearer and more precise, and first the Datasheet. The Reference Manual is going through the same process as well but is longer hence needs more time.

Sincerely, Naoum Gitnik.

Re: Exploring Vybrid A5 QSPI XIP performance

jackblather — Tue, 04 Mar 2014 19:46:04 GMT

I'm interested in this, too. Will there be an announcement when the new documents are released?

Re: Exploring Vybrid A5 QSPI XIP performance

naoumgitnik — Tue, 04 Mar 2014 20:32:28 GMT

Dear jackblather,

The whole discussion is about the F-Series (Industrial) version of Vybrid published last summer.

As I just learned, the R-Series (Automotive) Datasheet has been just published on the Freescale web site (where exactly, RossMcLuckie? - thanks!) and I was told that its timing diagrams were supposed to be the same as in the corrected F-Series one.

Regarding the official announcement about a new document revision publication - not sure, I doubt it...

Sincerely, Naoum Gitnik.

Nancy Jean Burkholder

Erick Castillo

Re: Exploring Vybrid A5 QSPI XIP performance

jackblather — Tue, 04 Mar 2014 20:48:31 GMT

Thanks. I didn't realize that thread was about the automotive variant. I'm developing with the VF6xx part. I will periodically check the FSL Vybrid pages for documentation updates.

Re: Exploring Vybrid A5 QSPI XIP performance

naoumgitnik — Tue, 04 Mar 2014 20:53:10 GMT

Jack,

I doubt the timing requirements are version-dependent.

BTW, the TWR-VF65GS10 board mentioned in the very beginning of the thread is based on the Industrial Vybrid variant.

Regards, Naoum Gitnik.

Re: Exploring Vybrid A5 QSPI XIP performance

erickcastillo — Tue, 04 Mar 2014 21:07:26 GMT

Hi Nancy,

Thanks for the comments. I edited my original reply to address the clock value typo; you are right.

I will shelf this until docs are out too I suppose. In the meantime, can you point me to any discussions that may have been posted here for the I-Cache set up? My interim solution is to transfer the image from QSPI to internal RAM but if you get even better performance via QSPI + I-Cache, I think I would prefer that route.

Thanks,

--Erick

Re: Exploring Vybrid A5 QSPI XIP performance

naoumgitnik — Tue, 04 Mar 2014 21:14:55 GMT

Hello Eric,

Have you tried using the 'Search' window in the upper right corner of the web page to find information you are looking for?

It is more convenient to be inside the Community space dedicated to your product of interest while doing that.

Regards, Naoum Gitnik.

Re: Exploring Vybrid A5 QSPI XIP performance

RossMcLuckie — Wed, 05 Mar 2014 10:38:56 GMT

Hi,

If you go to freescale.com and search for Vybrid Automotive you will return hits for the VF5xxR and VF3xxR web pages, these are the Vybrid auto parts and contain the new rev 6 R sereis datasheet. We are hopeful of releasing the F series very soon, but if you can't wait for that then the R version will give you an insight into what is coming, the majority of the content is the same, just be aware the 176QFP pinouts are different between the F and R families and only the R has GPU enabled parts.

For this specific issue, we have changed the spec to 80MHz SDR and 45MHz DDR maximum QuadSPI speeds. amh could you take a quick look at this thread and maybe advise, I think in the past you successfully ran the Tower QuadSPI at 80MHz SDR?

Thanks

Ross

Re: Exploring Vybrid A5 QSPI XIP performance

anthony_huereca — Wed, 05 Mar 2014 11:48:06 GMT

All the config info is in the sample code under \src\boot\quadspi\quadspi_boot.c and sometimes you might have to adjust the DDR sample point. I think I got it to 80MHhz,but jiri-b36968 did more on it in this regard.