topic Lowest Cost Boot Design ? in Vybrid Processors

Lowest Cost Boot Design ?

ChrisNielsen — Mon, 26 Aug 2013 14:01:20 GMT

I'm designing for a very cost sensitive application. I was planning to use low-end SPI NOR FLASH as my boot/storage device with no DDR external memory -- the on-board RAM (1MB) is sufficient for my data needs and my code will fit completely in the 512 KB cache.

The issue is that with "load and go" approach, I "waste" ~512KB of precious on-board RAM for my code's initial execution location which is useless since it is quickly pulled into cache and the 512 KB of RAM is never accessed again and I am left with 512 KB of RAM data space as opposed to a full 1 MB if I could execute in place (XIP).

>>> Or, is there a trick where I can lock all my code into cache then recover the 512 KB of initial code location and reuse it as data RAM?

So, I am studying all XIP options. I only see two listed: 1) Quad SPI, 2) Parallel NOR FLASH on FlexBus.

1) Quad SPI. My concern here is whether or not it is possible to boot from a single 4-bit wide (quad) SPI device. RM Table 19-9 seems to imply that two devices are required and the fact that the Tower board has two adds to my concern.

>>> So...is it possible to XIP from a single 4-bit SPI device?

Spansion S25FL032P is one example of a low-cost (<$0.60 @ 1K) quad SPI part that I am considering.

Thanks, Chris

Re: Lowest Cost Boot Design ?

ChrisNielsen — Mon, 26 Aug 2013 14:17:57 GMT

I forgot a key point. Low-end parallel NOR FLASH parts are in roughly the same price range as the Quad SPI parts for the same density (a bit of a premium for parallel's larger package).

The concern is the longer term pricing and availability of parallel NOR parts.

>>> I know it's a difficult question to answer but would you consider a design using parallel NOR a conservative move with the assumption that there will always be some smaller, aggresive silicon provider that will always provide parts in this classic deep embedded socket (parallel NOR)? (even if the cell phone OEMs move on to eMMC and drop all NOR. eMMC's lowest starting point is too costly for me)

Spansion has a long-term part program and Winbond and Macronix seems to be interested in this market and there are good supplies, today.

Thanks, Chris

Re: Lowest Cost Boot Design ?

ChrisNielsen — Mon, 26 Aug 2013 15:44:28 GMT

I did more reading in the RM. It appears that if QuadSPI1 is selected by BOOT_CFG[1], then it only has pads defined for a single quad SPI interface (4 data lines).

Table 19-12 shows a QuadSPI confirguarion parameter defining the "Mode of Operation" = Single, Dual, or Quad.

>>> Is it possible to XIP using a 1-bit SPI NOR part? (this assumes the initial 318 byte configuration fetch is always performed using the lowest common mode of 1-bit data)

In other words, can the QuadSPI XIP interface work in the degraded 1-bit mode?

Thanks, Chris

Re: Re: Lowest Cost Boot Design ?

naoumgitnik — Tue, 27 Aug 2013 16:52:02 GMT

Hello Chris,

There are 2 places in the Reference Manual where the QuadSPI XIP interface is mentioned:

Table 19-12 shows a QuadSPI configuration parameter defining the "Mode of Operation" = Single, Dual, or Quad.
In the “Memory Interfaces” description on page 2, it reads “Dual Quad SPI with XIP (Execute-In-Place)”.

It means the following:

The QuadSPI XIP interface work in the Single (1-bit data), Dual (2-bit data), or Quad (4-bit data) mode.
The “Memory Interfaces” description means that there are 2 QuadSPI controllers in Vybrid that can work in the XIP mode.

Regards, Naoum Gitnik.

Re: Lowest Cost Boot Design ?

ChrisNielsen — Tue, 27 Aug 2013 17:44:21 GMT

I'm sorry about the length of my questions above. I'll summarize the 2 core questions:

1) Is it possible to boot from a Single Quad SPI on QSPI0 or QSPI1? (as opposed to Dual Quad which is all that is ever mentioned in the marketing literature, DS, RM. The term Single Quad is never used. I'm rather confident it's supported, but I'd like to check since I'm spinning a board before we're able to test this area on Tower)

2) Is it possible to put a non-quad device (low-end 1-bit SPI FLASH) in a QSPI booting socket and have it boot? (I think all that matters is that it reads the first 318 bytes using 1-bit mode. It's really a question to clarify that it won't use some advanced Quad 1-bit communication method that older 1-bit SPI chips don't have)

Thanks, Chris

Re: Lowest Cost Boot Design ?

karina_valencia — Fri, 30 Aug 2013 21:03:48 GMT

naoumgitnik can you continue with the follow up of this case?

Re: Lowest Cost Boot Design ?

naoumgitnik — Tue, 03 Sep 2013 20:55:51 GMT

Hello Chris,

Without digging too dip, earlier you mentioned booting from the QSPI1 yourself ("... I did more reading in the RM. It appears that if QuadSPI1 is selected by BOOT_CFG[1]...") + there is a thread on the Community forum about booting via this bus.
Yes - apparently, if you are in the 1-bit mode, the other 3 bits are ignored. It is unclear what the "low-end" term means, but, as long as the bus specification is met by both the memory and the processor, everything is supposed to work.

Regards, Naoum Gitnik.

Re: Lowest Cost Boot Design ?

aleccohen — Fri, 18 Apr 2014 22:55:43 GMT

Hey Chris,

Looks like you already got your answer, but you might also look at the Macronix MX25L3235E (3V, 32Mb, Serial NOR Flash) which supports x1, x2, x4 I/O Read modes.

If you do not require x4, or the higher clock rates, you could look at the MX25L3206E which is even more cost effective.

-Regards, Alec