topic Re: TWR-VF65GS10 CTS/RTS connection in Vybrid Processors

TWR-VF65GS10 CTS/RTS connection

Hiroki — Wed, 05 Jun 2013 02:10:03 GMT

Hi,

TWR-VF65's SCI1 is connected with TWR-SER RS232C port.

However, SCI1_CTS/RTS are not connected with TWR-SER

CTS/RTS.　Instead SCI0_CTS/RTS are connected.

Why is TWR-VF65GS10 implemented like that? How can the

user use the flow control on the RS232C of TWR-SER?

Best Regards,

Hiroki

Re: TWR-VF65GS10 CTS/RTS connection

anthony_huereca — Wed, 05 Jun 2013 04:06:27 GMT

Hi Hiroki,

The reason is that the UART1 CTS/RTS signals were being used for other functionality as well as muxed with UART2 which is being used as the secondary UART option, and the main priority for both was basic UART functionality.

However as a work-around for flow control, you can simply connect B35 to B21 and B39 to A9 on the primary elevator side, which connects UART1 RTCS/CTS to the RTS and CTS pins of the TWR-SER respectively.

Re: TWR-VF65GS10 CTS/RTS connection

Hiroki — Wed, 05 Jun 2013 07:55:34 GMT

Hi Anthony,

Thank you for your reply.

I understand it.

Hiroki