topic Re: Using PLL5 for RMII-Clock in Vybrid Processors

Using PLL5 for RMII-Clock

slw — Mon, 03 Feb 2014 05:54:44 GMT

Hi,

I have a custom board with a PVF522R and a Ethernet-PHY using RMII.

I want to use the PLL5 as clock source for the internal MAC and the PHY (PTA6 / RMII_CLOKOUT).

First tests shown that data from Phy to MAC is working well, but data-transfer from MAC to PHY is not stable.

It seams that therre is something wrong with my settings cause the MAC puts data on the RMII on the falling edge of the RMII-Clock, not on the rising edge.

When I use a external clock for RMII and set PTA to RMII_CLKIN all works fine.

Any suggestions?

Or is there a problem cause the controller is a engineering sample ?

Regards

Re: Using PLL5 for RMII-Clock

Nouchi — Mon, 03 Feb 2014 09:31:32 GMT

Hello Sebastian,

Did you try to change SPEED/DSE parameters in IOMUXC_PTA6 register, it could help, maybe the signal is too "sluggish".

Re: Using PLL5 for RMII-Clock

slw — Mon, 03 Feb 2014 10:50:39 GMT

Hi,

Thanks for your answer.

I have tried different settings without success.

I can measure that the MAC puts his data on RMII at the wrong edge. The PHY reads data at the rising edge of the RMII-Clock.

But the MAC does change the data-lines at the rising edge. Which is wrong in my opinion.

The data-connection from PHY to MAC works correct.

Re: Using PLL5 for RMII-Clock

naoumgitnik — Mon, 03 Feb 2014 21:05:44 GMT

Dear Sebastian,

I tried to find where in our documentation the RMII clock phase is controlled, but :smileysad:, so I decided to approach the problem from the other end...

In one of our designs, Vybrid Automotive board, an RMII Etherent PHY is used, and Vybrid provides clock for it; thus, it makes sense to compare its settings to yours to find the difference.

timesyssupport, is there a way to share either those settings or simply a relevant piece of code (responsible for Ethernet / RMII) of the Vybrid Automotive board with the customer, please?

As far as I learned, it is a part of Uboot.

If, however, the code is considered confidential, please, provide all the information required for the customer to send a request to the local Freescale FAE.

Sincerely, Naoum Gitnik.

Re: Using PLL5 for RMII-Clock

timesyssupport — Tue, 04 Feb 2014 20:11:24 GMT

Hello Naoum,

In the u-boot sources supported by Timesys, version 2011.12, clocks are initialized in arch/arm/cpu/armv7/vybrid/lowlevel_init.S, in the init_clock macro.

Let me know if this helps.

Timesys Support

Re: Using PLL5 for RMII-Clock

naoumgitnik — Tue, 04 Feb 2014 23:53:39 GMT

Dear Timesys Support,

Thanks for your quick reply!

How can the customer get to this "u-boot source..., version 2011.12, ... in arch/arm/cpu/armv7/vybrid/lowlevel_init.S, ... init_clock macro", please?

Sincerely, Naoum Gitnik.

Re: Using PLL5 for RMII-Clock

timesyssupport — Wed, 05 Feb 2014 15:24:12 GMT

Hello Naoum,

The u-boot source can be found in any of the Starting Point builds for the Vybrid Tower published on LinuxLink:

https://linuxlink.timesys.com/download

For example, the u-boot source for the MCC Demo starting point can be found here:

https://linuxlink.timesys.com/build/viewBuildOutput.xhtml?buildId=39152&path=output/sources/u/u-boot/u-boot-2011.12

You would need to download and extract the source tarball, then apply the patch.

Alternatively, you can view the u-boot source for the Vybrid Tower via the public u-boot git tree hosted by Timesys. This requires a LinuxLink account to view:

https://linuxlink.timesys.com/git?repo=u-boot.git&view=tree&h=2011.12-mvf

Thanks,

Timesys Support

Re: Using PLL5 for RMII-Clock

naoumgitnik — Wed, 05 Feb 2014 16:45:05 GMT

Thanks a lot to timesyssupport for their help and clarification!

Dear Sebastian,

Please, let me know if this information helps to resolve the issue.

Sincerely, Naoum Gitnik.

Re: Using PLL5 for RMII-Clock

slw — Fri, 07 Feb 2014 08:12:55 GMT

Dear Naoum and Timsys-Support

Thanks for your fast response.

I have check several register-settings without success:

- PLL5 (ANADIG_PLL5_CTRL = 0x80002001)

- CCM (CCM_CSCDR1 = 0x01000000

CCM_CSCMR2 = 0x00000020)

- IOMUX (IOMUXC_PTA6 = 0x00102192

IOMUXC_PTC0 = 0x00103192

IOMUXC_PTC1 = 0x00103993

IOMUXC_PTC2 = 0x00103191

IOMUXC_PTC3 = 0x00103191

IOMUXC_PTC4 = 0x00103191

IOMUXC_PTC5 = 0x00103191

IOMUXC_PTC6 = 0x00103192

IOMUXC_PTC7 = 0x00103192

IOMUXC_PTC8 = 0x00103192

Do I have to check other registers too ??

Thanks

Re: Re: Using PLL5 for RMII-Clock

naoumgitnik — Fri, 07 Feb 2014 19:21:24 GMT

Dear Timesys Support,

Unfortunately, settings for the Vybrid Tower board are irrelevant in this case - Vybrid on this board uses external RMII Ethernet clock.

Relevant is the Vybrid Automotive (a.k.a. Auto) board, on which Vybrid provides clock for an Ethernet PHY (please, see my oroginal information).

Do you have code for it, please?

Sincerely, Naoum Gitnik.

Re: Re: Using PLL5 for RMII-Clock

slw — Mon, 10 Feb 2014 14:39:52 GMT

Hi Naoum,

The uboot-package above includes sources for the Vybrid Tower and the AutoEVB and

I have compared my own settings to the settings of the AutoEVB. But without success (see my posting from 07.02.2014)

Do you have a AutoEVB to make a measurement of the RMII-Clock and the TX-lines ?

Is there an difference between the engineering samples and the series production concerning the RMII-interface ?

Regards Sebastian

Re: Re: Re: Using PLL5 for RMII-Clock

naoumgitnik — Tue, 11 Feb 2014 18:55:35 GMT

Dear Sebastian,

As of now, I do not really have an Auto EVB on-hand to connect a scope to it, and before starting building and running this test setup (involving other people as well), I'd like to first understand what new we are expecting to see during this test.

The major point here is that the Ethernet PHY used on it (see datasheet attached) requires the same clock/data timing (data sampled on clock's rising edge) as yours, right? - Since both of them are based on the same RMII specification.

I am not a SW person, but is it possible to run our Auto EVB code on your board, even though some part of the IOs will be configured inappropriately for your board? - At least the Ethernet section will be configured fully identically to how it is on the Auto EVB.

Sincerely, Naoum Gitnik.

Re: Re: Re: Using PLL5 for RMII-Clock

slw — Wed, 19 Feb 2014 16:28:57 GMT

Dear Naoum,

Its not so easy to get the AutoEVB-Board running on our custom board.

I will try to get a AutoEVB-board from our official freescale-sales-partner to do further tests.

When there are some new results I'm gonna tell you.

Regards Sebastian

Re: Using PLL5 for RMII-Clock

jochengerster — Fri, 28 Feb 2014 08:44:11 GMT

Dear Mr Waldraff

thanks for your email

I had the same effect with the vybrid tower board with sporadic communication and the problem was that the PHY and the Vybrid drive the RMII clock at the same time.

Without knowing all details my first guess would be the same happens here as you also mentioned that if vybrid uses the RMII_CLK as an input it works but that definitely means the phy is driving the RMII clock

best regards

Jochen Gerster

Re: Using PLL5 for RMII-Clock

slw — Fri, 28 Feb 2014 09:01:49 GMT

Hello Mr. Gerster,

The Phy has a dedicated clock-input-pin (which we are using) and a dedicated clock-output-pin (which we left open as suggested in the datasheet of the phy).

So this cannot be the cause for the problem.

When I disable the RMII clock in the vybrid-cpu, there is no RMII clock signal.

Any other ideas ?

regards

Sebastian Waldraff

Re: Using PLL5 for RMII-Clock

jochengerster — Mon, 03 Mar 2014 13:38:28 GMT

Hello Mr. Waldraff

>>The Phy has a dedicated clock-input-pin (which we are using) and a dedicated clock-output-pin (which we left open as suggested in the datasheet of the phy).

I don't know the PHY and couldn't find the datasheet public - for me it is strange not having a direct clock between PHY and Vybrid on the RMII interface (no matter who is driving the clock)

I assume you try to save the external crystal for the phy?

This sounds like the PHY still drives the RMII clock out and so it need to be left open. I don't know how the PHY connects the clock input with the RMII clock out...

Have you compared the clock input with the not connected clock out?

best regards

Jochen Gerster

Re: Re: Using PLL5 for RMII-Clock

slw — Tue, 04 Mar 2014 10:07:20 GMT

Hello Mr. Gerster,

I have attached two diagramms which perhaps make it more clear. What we want is diagramm 1 and use the PTA6 as Clock_out to save external components as you assumed.

You can find the datasheet of the phy on http://www.microchip.com/wwwproducts/Devices.aspx?product=LAN8710A

best regards

S. Waldraff

Re: Re: Using PLL5 for RMII-Clock

naoumgitnik — Wed, 05 Mar 2014 00:51:14 GMT

Dear Sebastian,

I am still trying to get some other code examples for your case, will post here if find anything.

I reviewed the Vybrid-Phy.pdf file and am a bit confused by how the RXD and TXD pins are connected to each other - it should me the same name on both the MAC and PHY sides (e.g. see Figure 2 on page 16 of http://www.micrel.com/_PDF/Ethernet/datasheets/ksz8021rnl_8031rnl.pdf). Hopefully, the error is only in this illustrative document but not in the real design, otherwise nothing would work with any clocking scheme, right? (BTW, may you correct it in the same message, using 'Edit' option, to not confuse the others, please?)

BTW, from your PHY's datasheet, it is clear why it is working in the RX direction:

"3.4.2.2 Reference Clock (REF_CLK)

The RMII REF_CLK is a continuous clock that provides the timing reference for CRS_DV, RXD[1:0], TXEN, TXD[1:0] and RXER. The device uses REF_CLK as the network clock such that no buffering is required on the transmit data path. However, on the receive data path, the receiver recovers the clock from the incoming data stream, and the device uses elasticity buffering to accommodate for differences between the recovered clock and the local REF_CLK."

Please, keep me updated how your debugging is going.

Sincerely, Naoum Gitnik.

Re: Re: Re: Using PLL5 for RMII-Clock

naoumgitnik — Thu, 06 Mar 2014 18:42:23 GMT

Dear Sebastian,

Please, find some code, which hopefully will help you:

Clock & pad settings – Sysinit.c (function “sysinit”),
ENET register configurations selection - Enet_tests.c (function “functional_tests”),
ENET register settings – enet.c (function “enet_init”).

Sincerely, Naoum Gitnik.

Re: Re: Re: Re: Using PLL5 for RMII-Clock

slw — Wed, 26 Mar 2014 08:43:42 GMT

Dear Naoum,

Dear Mr. Gerster,

Now I have a Freescale AutoEVB-board and have done some measurements.

And you are right, I have mixed the description of rxd and txd.

I have attached the results of my mesaurements.

In my opinion, there is a bug inside the vybrid-cpu.

Regards

Sebastian