FlexBus burst mode question

johnfielden — Thu, 11 Jul 2013 21:49:48 GMT

Hi, I've looked over the reference manual and have a couple of questions about the FlexBus.

The only bus timings I see appear to show that all Flexbus signals must be qualified with the FB_CLK. Please confirm, Flexbus is not an asynchronous bus.

There are diagrams of 32 bit to 8 bit port burst (looks like 6 clocks min). But, I'm interested in doing a 32 bit to 16 bit port bursts. If I do 32 to 16, how many clock cycles is the access? 4? 5?

I was really hoping to burst several 32 bit words per cycles, but I don't see that listed. I'm assumming that idea is not possible.

Thanks,

John Fielden

Re: FlexBus burst mode question

naoumgitnik — Tue, 03 Sep 2013 22:44:10 GMT

Dear John,

According to the '32.4.7 Signal transitions' section, the bus is synchronous:

These signals change on the rising edge of the FlexBus clock (FB_CLK):

• Address

• Write data

• FB_TS/FB_ALE

• FB_CSn

• All attribute signals

FlexBus latches the read data on the rising edge of the clock.

May you refer me to the specific section and/or diagram that shows "32-bit to 8-bit port burst", please?

Sincerely, Naoum Gitnik.

topic Re: FlexBus burst mode question in Vybrid Processors

FlexBus burst mode question

Re: FlexBus burst mode question