Vybrid Cortex-M4 Cache - Controlling cacheability of different regions

zeeshanaslam — Mon, 16 Dec 2013 16:15:41 GMT

Hi,

I just want to quickly verify if there is any way to control the cacheability (write-back, write-through, non-cache) of different address space regions for Cortex-M4 core?

There are default cache modes at reset in Local Memory Controller (LMEM). What if I need different cache mode for DRAM address space? I understand that there is no MPU implemented for Vybrid. So where corresponding functionality exists for changing cacheability of memory, if at all? I don't see anything in SCU or anything else.

Or simply there is no way to control cacheability attributes of different address space regions for Vybrid CM4, right?

Thanks in advance,

Zeeshan Aslam

Re: Vybrid Cortex-M4 Cache - Controlling cacheability of different regions

rendy — Wed, 18 Dec 2013 14:20:27 GMT

Hello,

your last sentence is correct - controlling of cache modes is not possible on Vybrid's M4.

Rene

topic Vybrid Cortex-M4 Cache - Controlling cacheability of different regions in Vybrid Processors

Vybrid Cortex-M4 Cache - Controlling cacheability of different regions

Re: Vybrid Cortex-M4 Cache - Controlling cacheability of different regions