<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic PTB18 &amp; PTB19 in Vybrid Processors</title>
    <link>https://community.nxp.com/t5/Vybrid-Processors/PTB18-PTB19/m-p/261893#M1367</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The latest Version of Vybrid is 1.1, I believe that the Errata for 1.0 "System: Pins PTB18 and PTB19 need to be driven at boot." has been fixed, right?&lt;/P&gt;&lt;P&gt;And should I need to drive these two pins when boot from RCON mode on the Vybrid 1.1 chip?&lt;/P&gt;&lt;P&gt;Are there some things should I pay attention to when use the two ports as GPIO or alternative function?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Xuewei&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 11 Apr 2013 01:53:45 GMT</pubDate>
    <dc:creator>xueweiliu</dc:creator>
    <dc:date>2013-04-11T01:53:45Z</dc:date>
    <item>
      <title>PTB18 &amp; PTB19</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/PTB18-PTB19/m-p/261893#M1367</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The latest Version of Vybrid is 1.1, I believe that the Errata for 1.0 "System: Pins PTB18 and PTB19 need to be driven at boot." has been fixed, right?&lt;/P&gt;&lt;P&gt;And should I need to drive these two pins when boot from RCON mode on the Vybrid 1.1 chip?&lt;/P&gt;&lt;P&gt;Are there some things should I pay attention to when use the two ports as GPIO or alternative function?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Xuewei&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 11 Apr 2013 01:53:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/PTB18-PTB19/m-p/261893#M1367</guid>
      <dc:creator>xueweiliu</dc:creator>
      <dc:date>2013-04-11T01:53:45Z</dc:date>
    </item>
    <item>
      <title>Re: PTB18 &amp; PTB19</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/PTB18-PTB19/m-p/261894#M1368</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes, there is no longer a need to drive those pins on 1.1. They can be treated like any other GPIO. &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 11 Apr 2013 02:52:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/PTB18-PTB19/m-p/261894#M1368</guid>
      <dc:creator>anthony_huereca</dc:creator>
      <dc:date>2013-04-11T02:52:10Z</dc:date>
    </item>
    <item>
      <title>Re: PTB18 &amp; PTB19</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/PTB18-PTB19/m-p/261895#M1369</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 11 Apr 2013 06:05:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/PTB18-PTB19/m-p/261895#M1369</guid>
      <dc:creator>xueweiliu</dc:creator>
      <dc:date>2013-04-11T06:05:45Z</dc:date>
    </item>
  </channel>
</rss>

