topic Re: VF5xx/LPSTOPx mode in Vybrid Processors

VF5xx/LPSTOPx mode

soichiyamamoto — Fri, 26 Jul 2013 00:00:42 GMT

Hello,

Q1)

Please tell me the method to hold data of DDR3 or LPDDR2 in LPSTOPx mode.

Q2)

Please tell me the method to hold data of the internal RAM in LPSTOPx mode.

Best regards,

soichi yamamoto

Re: VF5xx/LPSTOPx mode

naoumgitnik — Tue, 30 Jul 2013 00:03:23 GMT

Dear Soichi,

The below text is to be added into our future Vybrid Tower board documentation:

Note regarding DDR3 Self-Refresh mode when Vybrid in LPStop modes:

* Not supported - as per Datasheet, DDR_RESET and DDR_CKE pins are in High-Z state in these modes.

* To add such support, following board modifications required:

1. Depopulate R107,

2. Add 10K pull-up to VCC_1V5 rail on DDR_RESET net,

3. Add 10K pull-down to GND rail on DDR_CKE net.

In this modes, only part of the memory contents can be retained - it is a good compromise to keep power consumption low.

Regards, Naoum Gitnik.

Re: Re: VF5xx/LPSTOPx mode

soichiyamamoto — Tue, 26 Nov 2013 01:59:50 GMT

Dear Naoum, Does IOConfiguration maintain it in LPSTOPx mode.? Best Regards, soichi yamamoto

Re: VF5xx/LPSTOPx mode

karina_valencia — Thu, 28 Nov 2013 18:48:22 GMT

naoumgitnik please continue with the follow up on this case.

Re: VF5xx/LPSTOPx mode

naoumgitnik — Tue, 03 Dec 2013 22:59:13 GMT

Dear Soichi,

Unfortunately, Vybrid is designed so that the pins' states are not controlled/retained in the LPStop modes; this is why external resistors are required (otherwise I would recommend you relevant settings...).

Regards, Naoum Gitnik.

Re: VF5xx/LPSTOPx mode

soichiyamamoto — Wed, 04 Dec 2013 00:56:03 GMT

Dear Naoum, Thank you for reply. Please tell me states of pin in LPStop modes? input or output? states of WKPU Pin ? Best regards, soichi

Re: VF5xx/LPSTOPx mode

naoumgitnik — Wed, 04 Dec 2013 20:25:55 GMT

"Dear Soichi,

As per the Datasheet, DDR_RESET and DDR_CKE pins are in High-Z state in these modes.
I am having difficulties understanding how the WKPU feature is related to DDR... but, according to the Reference Manual, '8.4.1 WKPU configuration' - "The table below [Table 8-4. WKUP Pins] shows the internal and external inputs to the WKUP module supported by the device.

Regards, Naoum Gitnik.

Re: VF5xx/LPSTOPx mode

soichiyamamoto — Thu, 05 Dec 2013 04:11:17 GMT

Dear Naoum, Please tell me about the status of IO except the DDR. Best Regards, soich,

Re: VF5xx/LPSTOPx mode

naoumgitnik — Fri, 06 Dec 2013 18:45:41 GMT

Dear Soichi,

This information is in the "14.3 Low-power modes" section, in "Table 14-2. Power gating and clock gating overview".

Briefly, they are in the High-Z state (the WKUP ones described separately, as I mentioned earlier - also see "14.3.7 Interrupt connectivity").

All the idea of LPSTOP modes is to save as much power as possible (this is why they are called "power-gating"), so a lot of power domains on the die are simply "powered off".

Regards, Naoum Gitnik.

Re: Re: VF5xx/LPSTOPx mode

soichiyamamoto — Mon, 09 Dec 2013 12:57:20 GMT

Dear Naoum,

Thank you for reply.

What is High-Z state?

Which Is IO Input or output?

Which Is Logic High or Low?

Best Regards,

soichi

Re: Re: VF5xx/LPSTOPx mode

naoumgitnik — Tue, 10 Dec 2013 15:24:29 GMT

Dear Soichi,

The definition is here - High impedance - Wikipedia, the free encyclopedia.

Regards, Naoum Gitnik.

Re: VF5xx/LPSTOPx mode

soichiyamamoto — Thu, 12 Dec 2013 09:37:31 GMT

Dear Naoum,

Thank you for reply.

Is Default of Kintis Pin same as High-Z state?

Best Regards,

soichi

Re: VF5xx/LPSTOPx mode

juan_mendoza — Thu, 12 Dec 2013 16:11:00 GMT

Hi Soichi,

The default for most Kinetis pins are to be tri-stated out of reset.

Regards,

Juan