topic Open drain Input to PTA17 in Vybrid Processors

Open drain Input to PTA17

tomokiokuno — Mon, 30 Sep 2013 03:01:11 GMT

Hi all,

We use PTA17(GPIO7) as open-drain input,and mount the external pull-up resistor of 10k Ohm.

The power supply is 3.3V same as VDD33 on Vybrid.

But, Hi level input to PTA17 will not be 3.3V.

We can see it about 1.0V.

We guess that there is a current leak path to ground,about 1k Ohm.

Off course, We checked the register settings,

IOMUXC_PTA17=0x2051

MUX_MODE=000, PUE=0, OBE=0, IBE=1.

We tried changing the register settings.

Only when we set to MUX_MODE=111(I2C), We can see Hi level 3.3V.

This behavior could also be seen in the PTB0 and PTC31 that we use as open-drain input as well.

We want you to find any errors in the circuit or register settings.

In our circuit, VDD12_AFE, VDDA33_AFE, VDDA33_ADC tie directly to ground,

as it is indicated in the reference manual.

Best Regards,

Tomoki

Re: Open drain Input to PTA17

naoumgitnik — Wed, 02 Oct 2013 00:11:33 GMT

Dear Tomoki,

Please, let me know if toggling the PUE and ODE bits helps.

Regards, Naoum Gitnik.

Re: Open drain Input to PTA17

tomokiokuno — Wed, 02 Oct 2013 04:41:24 GMT

Dear Naoum,

I tried toggling the PUE and ODE bit of IOMUXC_PTA17, but nothing changed.

When the OBE bit to Hi, Output was changed in accordance with the value of GPIO0_PDOR.

I think this behavior is causing a ESD protection diode on Vybrid.

Is there a ESD protection diode to VDDA33_ADC from PTA17?

It should be designed after the multiplexer.

Re: Open drain Input to PTA17

jiri-b36968 — Wed, 02 Oct 2013 09:08:24 GMT

Dear Tomoki san,

ESD protection is on every pin before any multiplexer. It is usually between Ground and VDD(A, IO-RING) or . It is protecting pin itself.

There is not any open drain input, but open drain output. If you want to use it as input in the same time you need to write to output buffer logical 1 GPIOx_PDOR (PTA17 equals to GPIO0[7] ). In that case output transistor will be closed and on the pin will be logical 1. You can tight it to the ground externally and monitor state of the pin in GPIOx_PDIR.

Your setting look like that you have not enabled OBE and ODE in the same time.

Generaly it is strange to tight VDDA to the groung if ADC unused because in Table 31 in Datasheet is mentioned:

delta VDD to VDDAD should be beween -100 and 100 mV.

/Jiri

Re: Open drain Input to PTA17

naoumgitnik — Wed, 02 Oct 2013 18:31:40 GMT

Hello Jiri,

Regarding connections of the VDDA power rails, I see the following logic in the Datasheet, which differentiates between 2 conditions, i.e. operating and unused:

Delta between analog VDDA and relevant digital VDD of -100 to 100 mV in the "12-bit ADC Operating Conditions" table,
Connecting to GND in the "Recommended Connections for Unused Analog Interfaces" table.

Regards, Naoum Gitnik.

Re: Open drain Input to PTA17

tomokiokuno — Thu, 03 Oct 2013 01:47:45 GMT

Dear Naoum and jiri,

My description was not enough, our circuit is as follows;

We use PTA17(GPIO7) as open-drain input

=>We use PTA17(GPIO7) as CMOS input, and on our circuit, We have put in there Open-drain Output from other device.

External pull-up resister is 10k Ohm, and the other device do not drive it Low.

Similar behavior occurs at PTB0 and PTC31, but does not occur at PTD11.

The common point of PTB0 and PTC31, they are multiplexed to the ADC.

In addition, Similar behavior does not occur in the evaluation board(TWR-VF65GS10), even if the same external circuit and same register set.

Defference between the evaluation board and our circuit is the connection of VDDA33_ADC.

We tight VDDA33_ADC to the ground in accordance with Recommended Connections for Unused Analog Interfaces, because we do not use the ADC.

Best Regards,

Tomoki

Re: Open drain Input to PTA17

naoumgitnik — Thu, 03 Oct 2013 18:04:26 GMT

Dear Tomoki,

There is no problem to connect the analog power rails to their digital counterparts, especially if you are going to copy our reference board.

To lower power consumption of the unused blocks, you may either control their power domains or gate the relevant clocks (details in the Reference Manual).

Jiri and myself discussed this issue today, and he gladly agreed to become a key support person for it.

Sincerely, Naoum Gitnik.

Re: Open drain Input to PTA17

tomokiokuno — Fri, 04 Oct 2013 02:36:23 GMT

Dear Naoum,

I'd like to know the following:

1. A description of the "Recommended Connections for Unused Analog Interfaces" of the refarence manual wrong?

2. In other pins, is there a similar probrem?(example, VDD12_AFE, VDDA33_AFE)

If it is wrong, then we fix the next prototype.

Best Regards,

Tomoki

Re: Open drain Input to PTA17

jiri-b36968 — Fri, 04 Oct 2013 05:02:45 GMT

Hello Tomoki,

it looks like that your issue is happening on pins which could be used as ADC inputs only. This is related to not powering ADC.

You are pointing to information in datasheet:

but there is also:

So content is king of inconsistent. The reason is probably ESD protection diodes. Working on that with designers and will let you know.

Please try to power ADC pins and not enable ADC from your application for now.

/Jiri

Re: Open drain Input to PTA17

tomokiokuno — Fri, 04 Oct 2013 08:18:11 GMT

Dear Jiri,

In the our board or Vybrid evaluation board, we will not be able to try it.

Because VDDA33_ADC is not out on the surface of those board.

In order that we do not fail in the next(final) prototype,

let me know the equivalent circuit around a protection diode and a multiplexer in Vybrid, and technical evidence.

Best Regards,

Tomoki

Re: Open drain Input to PTA17

naoumgitnik — Tue, 08 Oct 2013 20:40:37 GMT

Dear Tomoki,

As per data from another thread (https://community.freescale.com/thread/313484), it looks like it is not possible to tight the above-mentioned VDDAD to GND if unused.

Sorry for the typo (thanks for catching it!) - datasheet correction planned.

Regards, Naoum Gitnik.

Re: Open drain Input to PTA17

jiri-b36968 — Wed, 09 Oct 2013 08:26:12 GMT

Dear Tomoki-san,

I placed evidence into another thread Open drain question . It is not possible to publish it here - talked to your Freescale contact already. The issue is simply this: The channel MUX is inside ADC IP. It uses VADC33 for Nwell (PMOS body) therefore, GPIO input high will make this body diode of PMOS Forward Biased as VADC33 is grounded. So VDDAD has to be powered even ADC is not used. Recommended Connections for Unused Analog Interfaces in Datasheet is wrong (change initiated), but Table 12-bit ADC Operating Conditions is right.

I'm sorry for your troubles.

/Jiri