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<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>Embedded Software and Tools Clinic中的主题 HALL_XOR</title>
    <link>https://community.nxp.com/t5/Embedded-Software-and-Tools/HALL-XOR/m-p/1824539#M463</link>
    <description>&lt;P&gt;IN mkv31 HALL_XOR how to detect . i trying register level if any changes and anything configure guide me help for us.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="c"&gt;void initGPIO(void) {

    SIM-&amp;gt;SCGC5 |= SIM_SCGC5_PORTB_MASK;
    PORTB-&amp;gt;PCR[18] = PORT_PCR_MUX(3); // FTM2 channel 0
    PORTB-&amp;gt;PCR[19] = PORT_PCR_MUX(3); // FTM2 channel 1
    PORTB-&amp;gt;PCR[1] = PORT_PCR_MUX(3);  // FTM1 channel 1

    SIM-&amp;gt;SCGC5 |= SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTE_MASK;
    //PORTC-&amp;gt;PCR[6] = PORT_PCR_MUX(1); // GPIO
    //GPIOC-&amp;gt;PDDR |= (1U &amp;lt;&amp;lt; 6);        // Set as output

    //PORTE-&amp;gt;PCR[6] = PORT_PCR_MUX(1); // GPIO
    //GPIOE-&amp;gt;PDDR |= (1U &amp;lt;&amp;lt; 6);
}




void initInputCapture(void) {
    SIM-&amp;gt;SCGC6 |= SIM_SCGC6_FTM1_MASK | SIM_SCGC6_FTM2_MASK;
    FTM1-&amp;gt;MODE |= FTM_MODE_WPDIS_MASK;
    FTM2-&amp;gt;MODE |= FTM_MODE_WPDIS_MASK;

    FTM1-&amp;gt;MOD = 0xFFFF;
    FTM2-&amp;gt;MOD = 0xFFFF;
        FTM2-&amp;gt;COMBINE |= FTM_COMBINE_DECAPEN0_MASK; // Assuming this enables XOR on FTM2 CH0 and CH1
          SIM-&amp;gt;SOPT4 |= SIM_SOPT4_FTM2CH1SRC_MASK;
    FTM2-&amp;gt;CONTROLS[0].CnSC = FTM_CnSC_CHIE_MASK | FTM_CnSC_ELSA_MASK;
    FTM2-&amp;gt;CONTROLS[1].CnSC = FTM_CnSC_CHIE_MASK | FTM_CnSC_ELSA_MASK;
    FTM1-&amp;gt;CONTROLS[1].CnSC = FTM_CnSC_CHIE_MASK | FTM_CnSC_ELSA_MASK;
    FTM2-&amp;gt;SC |= FTM_SC_TOIE_MASK;
    FTM1-&amp;gt;SC |= FTM_SC_TOIE_MASK;
    NVIC_EnableIRQ(FTM2_IRQn);
    NVIC_EnableIRQ(FTM1_IRQn);

    FTM2-&amp;gt;SC = FTM_SC_CLKS(1) | FTM_SC_PS(0);
    FTM1-&amp;gt;SC = FTM_SC_CLKS(1) | FTM_SC_PS(0);
}


void FTM2_IRQHandler(void) {

	if (FTM2-&amp;gt;SC &amp;amp; FTM_SC_TOF_MASK) {
	        FTM2-&amp;gt;SC &amp;amp;= ~FTM_SC_TOF_MASK; // Clear the overflow flag
	        GPIO_PortToggle(GPIOC, 1U &amp;lt;&amp;lt; 6); // Example: Toggle GPIOC pin 6 for overflow visualization
	    }
    if(FTM2-&amp;gt;CONTROLS[0].CnSC &amp;amp; FTM_CnSC_CHF_MASK) {
        GPIO_PortClear(GPIOC, 1U &amp;lt;&amp;lt; 6);
        a+=b;
        FTM2-&amp;gt;CONTROLS[0].CnSC &amp;amp;= ~FTM_CnSC_CHF_MASK; // Clear flag
        GPIO_PortClear(GPIOC, 1U &amp;lt;&amp;lt; 6);
    }
    if(FTM2-&amp;gt;CONTROLS[1].CnSC &amp;amp; FTM_CnSC_CHF_MASK) {

        GPIO_PortClear(GPIOC, 1U &amp;lt;&amp;lt; 6);
        FTM2-&amp;gt;CONTROLS[1].CnSC &amp;amp;= ~FTM_CnSC_CHF_MASK; // Clear flag
        GPIO_PortClear(GPIOC, 1U &amp;lt;&amp;lt; 6);
    }
    GPIO_PortClear(GPIOC, 1U &amp;lt;&amp;lt; 6);
}


void FTM1_IRQHandler(void) {
    // Handle input capture for FTM1 CH1
    if(FTM1-&amp;gt;CONTROLS[1].CnSC &amp;amp; FTM_CnSC_CHF_MASK) {
        GPIO_PortClear(GPIOE, 1U &amp;lt;&amp;lt; 6);
        FTM1-&amp;gt;CONTROLS[1].CnSC &amp;amp;= ~FTM_CnSC_CHF_MASK; // Clear flag
        GPIO_PortClear(GPIOE, 1U &amp;lt;&amp;lt; 6);
    }
}&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; Thankyou&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;PANDI&lt;/P&gt;</description>
    <pubDate>Sat, 09 Mar 2024 12:27:59 GMT</pubDate>
    <dc:creator>pandi</dc:creator>
    <dc:date>2024-03-09T12:27:59Z</dc:date>
    <item>
      <title>HALL_XOR</title>
      <link>https://community.nxp.com/t5/Embedded-Software-and-Tools/HALL-XOR/m-p/1824539#M463</link>
      <description>&lt;P&gt;IN mkv31 HALL_XOR how to detect . i trying register level if any changes and anything configure guide me help for us.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="c"&gt;void initGPIO(void) {

    SIM-&amp;gt;SCGC5 |= SIM_SCGC5_PORTB_MASK;
    PORTB-&amp;gt;PCR[18] = PORT_PCR_MUX(3); // FTM2 channel 0
    PORTB-&amp;gt;PCR[19] = PORT_PCR_MUX(3); // FTM2 channel 1
    PORTB-&amp;gt;PCR[1] = PORT_PCR_MUX(3);  // FTM1 channel 1

    SIM-&amp;gt;SCGC5 |= SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTE_MASK;
    //PORTC-&amp;gt;PCR[6] = PORT_PCR_MUX(1); // GPIO
    //GPIOC-&amp;gt;PDDR |= (1U &amp;lt;&amp;lt; 6);        // Set as output

    //PORTE-&amp;gt;PCR[6] = PORT_PCR_MUX(1); // GPIO
    //GPIOE-&amp;gt;PDDR |= (1U &amp;lt;&amp;lt; 6);
}




void initInputCapture(void) {
    SIM-&amp;gt;SCGC6 |= SIM_SCGC6_FTM1_MASK | SIM_SCGC6_FTM2_MASK;
    FTM1-&amp;gt;MODE |= FTM_MODE_WPDIS_MASK;
    FTM2-&amp;gt;MODE |= FTM_MODE_WPDIS_MASK;

    FTM1-&amp;gt;MOD = 0xFFFF;
    FTM2-&amp;gt;MOD = 0xFFFF;
        FTM2-&amp;gt;COMBINE |= FTM_COMBINE_DECAPEN0_MASK; // Assuming this enables XOR on FTM2 CH0 and CH1
          SIM-&amp;gt;SOPT4 |= SIM_SOPT4_FTM2CH1SRC_MASK;
    FTM2-&amp;gt;CONTROLS[0].CnSC = FTM_CnSC_CHIE_MASK | FTM_CnSC_ELSA_MASK;
    FTM2-&amp;gt;CONTROLS[1].CnSC = FTM_CnSC_CHIE_MASK | FTM_CnSC_ELSA_MASK;
    FTM1-&amp;gt;CONTROLS[1].CnSC = FTM_CnSC_CHIE_MASK | FTM_CnSC_ELSA_MASK;
    FTM2-&amp;gt;SC |= FTM_SC_TOIE_MASK;
    FTM1-&amp;gt;SC |= FTM_SC_TOIE_MASK;
    NVIC_EnableIRQ(FTM2_IRQn);
    NVIC_EnableIRQ(FTM1_IRQn);

    FTM2-&amp;gt;SC = FTM_SC_CLKS(1) | FTM_SC_PS(0);
    FTM1-&amp;gt;SC = FTM_SC_CLKS(1) | FTM_SC_PS(0);
}


void FTM2_IRQHandler(void) {

	if (FTM2-&amp;gt;SC &amp;amp; FTM_SC_TOF_MASK) {
	        FTM2-&amp;gt;SC &amp;amp;= ~FTM_SC_TOF_MASK; // Clear the overflow flag
	        GPIO_PortToggle(GPIOC, 1U &amp;lt;&amp;lt; 6); // Example: Toggle GPIOC pin 6 for overflow visualization
	    }
    if(FTM2-&amp;gt;CONTROLS[0].CnSC &amp;amp; FTM_CnSC_CHF_MASK) {
        GPIO_PortClear(GPIOC, 1U &amp;lt;&amp;lt; 6);
        a+=b;
        FTM2-&amp;gt;CONTROLS[0].CnSC &amp;amp;= ~FTM_CnSC_CHF_MASK; // Clear flag
        GPIO_PortClear(GPIOC, 1U &amp;lt;&amp;lt; 6);
    }
    if(FTM2-&amp;gt;CONTROLS[1].CnSC &amp;amp; FTM_CnSC_CHF_MASK) {

        GPIO_PortClear(GPIOC, 1U &amp;lt;&amp;lt; 6);
        FTM2-&amp;gt;CONTROLS[1].CnSC &amp;amp;= ~FTM_CnSC_CHF_MASK; // Clear flag
        GPIO_PortClear(GPIOC, 1U &amp;lt;&amp;lt; 6);
    }
    GPIO_PortClear(GPIOC, 1U &amp;lt;&amp;lt; 6);
}


void FTM1_IRQHandler(void) {
    // Handle input capture for FTM1 CH1
    if(FTM1-&amp;gt;CONTROLS[1].CnSC &amp;amp; FTM_CnSC_CHF_MASK) {
        GPIO_PortClear(GPIOE, 1U &amp;lt;&amp;lt; 6);
        FTM1-&amp;gt;CONTROLS[1].CnSC &amp;amp;= ~FTM_CnSC_CHF_MASK; // Clear flag
        GPIO_PortClear(GPIOE, 1U &amp;lt;&amp;lt; 6);
    }
}&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; Thankyou&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;PANDI&lt;/P&gt;</description>
      <pubDate>Sat, 09 Mar 2024 12:27:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Embedded-Software-and-Tools/HALL-XOR/m-p/1824539#M463</guid>
      <dc:creator>pandi</dc:creator>
      <dc:date>2024-03-09T12:27:59Z</dc:date>
    </item>
    <item>
      <title>Re: HALL_XOR</title>
      <link>https://community.nxp.com/t5/Embedded-Software-and-Tools/HALL-XOR/m-p/1825152#M464</link>
      <description>&lt;P&gt;HI&lt;/P&gt;&lt;P&gt;Every one if anyone know how to configure HALL SENSOR_XOR method in mkv31f512vll12?&lt;/P&gt;</description>
      <pubDate>Mon, 11 Mar 2024 12:09:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Embedded-Software-and-Tools/HALL-XOR/m-p/1825152#M464</guid>
      <dc:creator>pandi</dc:creator>
      <dc:date>2024-03-11T12:09:58Z</dc:date>
    </item>
  </channel>
</rss>

