topic T1022 Secure Boot in T-Series

T1022 Secure Boot

tschutte — Wed, 08 Jun 2016 18:40:02 GMT

So After being able to get the secureboot process working on a P4080, I am trying to set things up on a T series processor.

Here is what I have so far:

Created OTPMK and programmed, Created SRKH and programmed, Checked for OTPMK errors - none found - before moving onto setting up the RCW. In the RCW; set SB_EN bit, created LAW (Based on working LAW from p4080, addr is known to be in first 3.5Gb, set SCRATCHRW1 with location of CSF. Sign U-Boot with CST 2.0, and program board with U-boot and CST at addresses. Currently the board goes into a machine check (0x1 in SCRATCHRW2) so I think there might be an issue with a PBL / RCW command I am issuing. But looking at example ESBC LAW's from SDK 2.0 doc and prior I look to be doing things correctly. Is there something else I may be missing?

Re: T1022 Secure Boot

tschutte — Wed, 15 Jun 2016 16:01:13 GMT

0x1

ERROR_MACHINECHECK

Machine check Exception

is the error in SRATCHRW2 specifically.... While I can set SB_EN to 0 and boot just fine, the second that bit is flipped I get nowhere... Thoughts?

Re: T1022 Secure Boot

bpe — Tue, 21 Jun 2016 13:40:07 GMT

Error 0x1 is reported only for machine checks. Try reading registers

mentioned in 13.3.1.3.2 of T1040RM to determine where it occurs.

Make sure SCRATCHRW1 and CSF header contain valid addresses.

SDK 2.0 provides a working secure boot scenario for T1042RDB. If you

are working with the RDB, try it first. If you are working with a

custom board, study the existing configuration and make minimum required

changes.

Detailed instructions can be found here:

https://freescale.sdlproducts.com/LiveContent/content/en-US/QorIQ_SDK/GUID-038CFEAB-F051-46F9-94E6-F57419C9557E

Have a great day,
Platon

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Re: T1022 Secure Boot

keithartel — Wed, 08 Feb 2017 14:35:36 GMT

Hi, I'm picking up the work Tom was doing with Secure Boot on the T1022. I can get secure boot working as a monolithic secure boot, but I'd like to know how to use secure boot with stages. How does the ESBC Boot script get kicked off? I'm trying to figure out what I need to configure in order for the boot script to be implemented.

Also, the documentation says that the boot script validates 3 additional images. Does it have to be 3? Can it be less? For example, I'm working with VxWorks, and I only have two additional images - the DTB and the kernel. How would I write the script in that case?

Thanks,

Keith

Re: T1022 Secure Boot

ravirajaram — Tue, 22 May 2018 20:40:15 GMT

Hi Keith,

You mentioned that you were able to get past the original problem (0x01 in SCRATCHRW2 indicating Critical Exception during ISBC Phase) on your system. May I know what the root cause of the exception was and how it was fixed on your system?

Thanks & Regards,

Ravi.

Re: T1022 Secure Boot

keithartel — Wed, 23 May 2018 13:22:17 GMT

The root cause of my issue was that I ran into an erratum where I was booting my U-Boot from NOR flash with the RCW stored in a non-NOR flash source. The erratum is specific to this particular scenario.

If you want more details on the erratum, you'll need to contact NXP since I'm not an employee of NXP.

Re: T1022 Secure Boot

ravirajaram — Wed, 23 May 2018 17:38:31 GMT

Hi Keith,

Thanks for your response. The system I am working on has a similar scheme - u-boot in NOR and RCW in non-NOR flash source. I will contact NXP support to check if this erratum applies for the scenario I have.

Thanks again.

Regards,

Ravi.

Re: T1022 Secure Boot

bob_behrooz — Wed, 23 May 2018 18:37:17 GMT

Hi Keith,

Could you please identify the erratum number or specifics of the erratum that affected you? I reviewed T1040 Chip Erratum Rev. 5, 12/2017 and can not find an erratum that matches your description.

Regards,

Bob

Re: T1022 Secure Boot

keithartel — Wed, 23 May 2018 19:10:22 GMT

Bob,

The erratum that was pointed to me A-009950 that is in the LS2080A and LS2040A Chip Errata document titled "IFC is not automatically initialized according to RCW[FLASH_MODE] if IFC is not the RCW source".

My NXP Field contact at the time told me that this erratum was discovered after the last errata was published but it does apply to the T1022. Once I apply that erratum fix, I can get Secure Boot working.

I found that I also need to do this on a T2080 and other Trust Architecture 2.0 products as well, as most of my company's products have the RCW in SPI flash while our U-Boot is in NOR flash.

Keith

Re: T1022 Secure Boot

keithartel — Wed, 23 May 2018 19:51:59 GMT

I'm guessing it will. I was told that it applies to all Trust Architecture 2.0 products. I've only tried this on a T1022 and T2080, and both needed this erratum.

Re: T1022 Secure Boot

ravirajaram — Thu, 24 May 2018 22:38:10 GMT

Hi Keith,

Thanks a lot for your inputs and sharing the details of the fix. Bob provided a RCW/PBL image with this workaround and it seems to get past the exception issue now.

Regards,

Ravi.