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<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
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    <title>topic Re: T2080RDB-PC Changes  in T-Series</title>
    <link>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508648#M910</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;gt; The one at ec000000 is used at boot time.&lt;/P&gt;&lt;P&gt;Is the board able to boot pre-installed U-Boot?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 31 Mar 2016 12:44:49 GMT</pubDate>
    <dc:creator>ufedor</dc:creator>
    <dc:date>2016-03-31T12:44:49Z</dc:date>
    <item>
      <title>T2080RDB-PC Changes</title>
      <link>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508637#M899</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;What were the MAJOR changes from the T2080RDB-PA to the T2080RDB-PC?&lt;/P&gt;&lt;P&gt;I'm trying to get the VxWorks 6.9 bootrom to launch with no luck.&lt;/P&gt;&lt;P&gt;The target.ref indicates that the BSP was tested on the T2080RDB-PA (Rev A).&amp;nbsp; I have a Rev C RDB.&lt;/P&gt;&lt;P&gt;Are there any memory mapping or major changes that might lead to this BSP totally malfunctioning?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 28 Mar 2016 21:23:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508637#M899</guid>
      <dc:creator>elsasnow</dc:creator>
      <dc:date>2016-03-28T21:23:55Z</dc:date>
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    <item>
      <title>Re: T2080RDB-PC Changes</title>
      <link>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508638#M900</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Main difference is the silicon revision change from 1.0 to 1.1.&lt;/P&gt;&lt;P&gt;Please note that the revisions have different descriptions for the RCW[MEM_PLL_RAT].&lt;/P&gt;&lt;P&gt;Please ask Wind River for updated RCW.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 29 Mar 2016 02:23:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508638#M900</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2016-03-29T02:23:21Z</dc:date>
    </item>
    <item>
      <title>Re: T2080RDB-PC Changes</title>
      <link>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508639#M901</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I received word from Wind River that they can boot the Rev B version of this board with no issue (T2080RDB-PB).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Would the same recommendation apply regarding the RCW changes when going from Rev B to Rev C?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In other words, the RCW in my Rev C board should match what Wind River has in their Rev B?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 29 Mar 2016 13:09:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508639#M901</guid>
      <dc:creator>elsasnow</dc:creator>
      <dc:date>2016-03-29T13:09:32Z</dc:date>
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    <item>
      <title>Re: T2080RDB-PC Changes</title>
      <link>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508640#M902</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes.&lt;/P&gt;&lt;P&gt;T2080RDB-PB also has silicon 1.1.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 29 Mar 2016 13:20:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508640#M902</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2016-03-29T13:20:53Z</dc:date>
    </item>
    <item>
      <title>Re: T2080RDB-PC Changes</title>
      <link>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508641#M903</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I will try to get the Wind River RCW.&lt;/P&gt;&lt;P&gt;I'm using Rev C&lt;/P&gt;&lt;P&gt;Wind River is using Rev B.&lt;/P&gt;&lt;P&gt;Their T2080RDB can boot VxW, but mine cannot.&lt;/P&gt;&lt;P&gt;It hangs when I select the alternate bank after switching SW3.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 29 Mar 2016 13:46:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508641#M903</guid>
      <dc:creator>elsasnow</dc:creator>
      <dc:date>2016-03-29T13:46:51Z</dc:date>
    </item>
    <item>
      <title>Re: T2080RDB-PC Changes</title>
      <link>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508642#M904</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'd like to rephrase the original question based on the feedback I've received from Wind River.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P style="font-size: 14px; font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;&lt;/P&gt;&lt;P style="font-size: 14px; font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;What were the MAJOR changes from the &lt;STRONG&gt;T2080RDB-PB&lt;/STRONG&gt; to the &lt;STRONG&gt;T2080RDB-PC&lt;/STRONG&gt;?&lt;/P&gt;&lt;P style="font-size: 14px; font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;I'm trying to get the VxWorks 6.9 bootrom to launch on a Rev C T2080RDB with no luck.&lt;/P&gt;&lt;P style="font-size: 14px; font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;WindRiver was able to get a bootrom to work on their Rev B device.&lt;/P&gt;&lt;P style="font-size: 14px; font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;Are there any memory mapping, RCW, or major changes that might lead to this BSP totally malfunctioning when moving the Rev B BSP to a Rev C T2080RDB?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 30 Mar 2016 18:13:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508642#M904</guid>
      <dc:creator>elsasnow</dc:creator>
      <dc:date>2016-03-30T18:13:43Z</dc:date>
    </item>
    <item>
      <title>Re: T2080RDB-PC Changes</title>
      <link>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508643#M905</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Sorry, there was a typo in my previous response.&lt;/P&gt;&lt;P&gt;Corrected statement is:&lt;/P&gt;&lt;P&gt;T2080RDB-PB also has silicon 1.0.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Major details of the RDB revisions:&lt;/P&gt;&lt;P&gt;PA&amp;nbsp; =&amp;nbsp; rev. 1.0 Si, did not support SRIOV on PCIe controller assigned to the gold fingers; SDK 1.5 ; CPU = 1.533GHz; DDR=1.6GHz&lt;/P&gt;&lt;P&gt;&lt;SPAN class="&amp;amp;quothighlight&amp;quot;"&gt;PB&lt;/SPAN&gt; =&amp;nbsp; rev. 1.0 Si, relayed out board to route SRIOV enable PCIe controller to gold finger; SDK 1.6 ; CPU=1.533GHz; DDR=1.6GHz&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;&lt;SPAN class="&amp;amp;quothighlight&amp;quot;"&gt;PC&lt;/SPAN&gt; = rev 1.1&lt;/STRONG&gt; Si.&amp;nbsp; Latest SDK 1.7 ; CPU=1.8GHz ; DDR=1.867GHz&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 31 Mar 2016 01:53:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508643#M905</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2016-03-31T01:53:06Z</dc:date>
    </item>
    <item>
      <title>Re: T2080RDB-PC Changes</title>
      <link>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508644#M906</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I understand the CPU speed and DDR clock changes.&lt;/P&gt;&lt;P&gt;Regarding "Si" revision, are you referring to the CPU itself going from revision 1.0 to 1.1?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If I was to apply the RCW used by Wind River for the Rev B T2080RDB, would that possibly remedy the boot problem when using the Rev C RDB board?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 31 Mar 2016 12:09:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508644#M906</guid>
      <dc:creator>elsasnow</dc:creator>
      <dc:date>2016-03-31T12:09:50Z</dc:date>
    </item>
    <item>
      <title>Re: T2080RDB-PC Changes</title>
      <link>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508645#M907</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;gt; Regarding "Si" revision, are you referring to the CPU itself going from revision 1.0 to 1.1?&lt;/P&gt;&lt;P&gt;Yes.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The RCW[MEM_PLL_RAT] has to be specified differently for the T2080 silicon revision 1.0 and 1.1. (Correct options of the MEM_PLL_RAT for the silicon rev.1.1 are provided in the T2080 RM available at: &lt;A href="http://www.nxp.com/products/microcontrollers-and-processors/power-architecture-processors/qoriq-power-architecture-processors/qoriq-t2080-and-t2081-multicore-communications-processors:T2080?fpsp=1&amp;amp;tab=Documentation_Tab&amp;amp;lang_cd=en" title="http://www.nxp.com/products/microcontrollers-and-processors/power-architecture-processors/qoriq-power-architecture-processors/qoriq-t2080-and-t2081-multicore-communications-processors:T2080?fpsp=1&amp;amp;tab=Documentation_Tab&amp;amp;lang_cd=en"&gt;QorIQ T2080 and T2081 Multicore Communication|NXP&lt;/A&gt; )&lt;/P&gt;&lt;P&gt;So answer to your question is - No.&lt;/P&gt;&lt;P&gt;I.e. RCW for T2080RDB-PB will not work on the T2080RDB-PC.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 31 Mar 2016 12:19:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508645#M907</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2016-03-31T12:19:35Z</dc:date>
    </item>
    <item>
      <title>Re: T2080RDB-PC Changes</title>
      <link>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508646#M908</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;If the BSP in question contains binary image of the RCW I could "convert" it for the silicon revision 1.1.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 31 Mar 2016 12:23:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508646#M908</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2016-03-31T12:23:24Z</dc:date>
    </item>
    <item>
      <title>Re: T2080RDB-PC Changes</title>
      <link>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508647#M909</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;My understanding is that the RCW is NOT contained within the bootrom.&amp;nbsp; The one at ec000000 is used at boot time.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm working with both NXP and Wind River on this.&amp;nbsp; My goal is to try and find if the BSP needs a change to support the Rev C board (with the assumption that it works fine on the Rev B board).&amp;nbsp; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We keep coming back to RCW[MEM_PLL_RAT] as a delta.&amp;nbsp; Is this potentially something I would need to adjust in the RCW in order to get the VxW bootrom to load?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;My goal at this point is to determine if the bootrom needs a change or the RCW needs a change to account for the hardware changes from Rev B to C.&lt;/P&gt;&lt;P&gt;Thanks!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 31 Mar 2016 12:32:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508647#M909</guid>
      <dc:creator>elsasnow</dc:creator>
      <dc:date>2016-03-31T12:32:56Z</dc:date>
    </item>
    <item>
      <title>Re: T2080RDB-PC Changes</title>
      <link>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508648#M910</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;gt; The one at ec000000 is used at boot time.&lt;/P&gt;&lt;P&gt;Is the board able to boot pre-installed U-Boot?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 31 Mar 2016 12:44:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508648#M910</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2016-03-31T12:44:49Z</dc:date>
    </item>
    <item>
      <title>Re: T2080RDB-PC Changes</title>
      <link>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508649#M911</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes.&amp;nbsp; I'm able to boot U-Boot from vbank0 and vbank4 using SW3 adjustment.&lt;/P&gt;&lt;P&gt;I'm putting the VxW bootrom at ebf00000, then adjusting SW3 accordingly to select vbank4.&lt;/P&gt;&lt;P&gt;The RCW is untouched from what was originally programmed in the board at factory.&lt;/P&gt;&lt;P&gt;Doing this causes the board to hang at boot. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Wind River uses these same steps on a Rev B board, and the bootrom properly loads.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 31 Mar 2016 13:07:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508649#M911</guid>
      <dc:creator>elsasnow</dc:creator>
      <dc:date>2016-03-31T13:07:51Z</dc:date>
    </item>
    <item>
      <title>Re: T2080RDB-PC Changes</title>
      <link>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508650#M912</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;gt; I'm putting the VxW bootrom at ebf00000, then adjusting SW3 accordingly to select vbank4.&lt;/P&gt;&lt;P&gt;Is the VxW bootrom address really 0xebf00000?&lt;/P&gt;&lt;P&gt;What is the bootrom binary size?&lt;/P&gt;&lt;P&gt;May be it is needed to select another vbank?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 31 Mar 2016 13:36:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T2080RDB-PC-Changes/m-p/508650#M912</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2016-03-31T13:36:09Z</dc:date>
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  </channel>
</rss>

