<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: INTLVEN for T1040RDB in T-Series</title>
    <link>https://community.nxp.com/t5/T-Series/INTLVEN-for-T1040RDB/m-p/479855#M633</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Interleaving may be used only if you have two CPC sram memories. In case of P4080 there are two CPC blocks, but in T1040 there is only one CPC block, so there is nothing to interleave with.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Alexander&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 18 May 2016 06:25:52 GMT</pubDate>
    <dc:creator>alexander_yakov</dc:creator>
    <dc:date>2016-05-18T06:25:52Z</dc:date>
    <item>
      <title>INTLVEN for T1040RDB</title>
      <link>https://community.nxp.com/t5/T-Series/INTLVEN-for-T1040RDB/m-p/479854#M632</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I found in the P4080RM the ability to interleave SRAM address space by setting CPCSRCR0[INTLVEN] bit.&amp;nbsp; But the INTLVEN bit is not defined in the T1040RM.&amp;nbsp; Does that mean I can't interleave SRAM in the T1040?&amp;nbsp; Thanks!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 17 May 2016 15:11:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/INTLVEN-for-T1040RDB/m-p/479854#M632</guid>
      <dc:creator>hv</dc:creator>
      <dc:date>2016-05-17T15:11:28Z</dc:date>
    </item>
    <item>
      <title>Re: INTLVEN for T1040RDB</title>
      <link>https://community.nxp.com/t5/T-Series/INTLVEN-for-T1040RDB/m-p/479855#M633</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Interleaving may be used only if you have two CPC sram memories. In case of P4080 there are two CPC blocks, but in T1040 there is only one CPC block, so there is nothing to interleave with.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Alexander&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 18 May 2016 06:25:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/INTLVEN-for-T1040RDB/m-p/479855#M633</guid>
      <dc:creator>alexander_yakov</dc:creator>
      <dc:date>2016-05-18T06:25:52Z</dc:date>
    </item>
    <item>
      <title>Re: INTLVEN for T1040RDB</title>
      <link>https://community.nxp.com/t5/T-Series/INTLVEN-for-T1040RDB/m-p/479856#M634</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 18 May 2016 12:13:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/INTLVEN-for-T1040RDB/m-p/479856#M634</guid>
      <dc:creator>hv</dc:creator>
      <dc:date>2016-05-18T12:13:37Z</dc:date>
    </item>
  </channel>
</rss>

