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    <title>topic T2080 cache partition in T-Series</title>
    <link>https://community.nxp.com/t5/T-Series/T2080-cache-partition/m-p/478944#M628</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear All&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am going to devlop the system by using T2080 and VxWorks 653 3.0 version.&lt;/P&gt;&lt;P&gt;I will use the fsl_t2080_qds evaluation board from freescale.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Question 1&amp;gt;&lt;/P&gt;&lt;P&gt;The L2 cahe of T2080 is shared among foru physical cores.&lt;/P&gt;&lt;P&gt;Is there any way to partition the L2 Cache to each core??&lt;/P&gt;&lt;P&gt;Please let me know how to do that.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Question 2&amp;gt;&lt;/P&gt;&lt;P&gt;There are two memac ports (memac 2 and memac 3) in t2080 QDS board.&lt;/P&gt;&lt;P&gt;I want to test different network configuration with this board.&lt;/P&gt;&lt;P&gt;First, I want to configure that&amp;nbsp; only one core can hanle tow memac ports.&lt;/P&gt;&lt;P&gt;What shall I do this?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Second, I also wanto to configure that first core hansles memac2, and second core handles memac3, respectively.&lt;/P&gt;&lt;P&gt;What shall I do this?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Third, If I want to add another memac port, like memac4.&lt;/P&gt;&lt;P&gt;What shall I do this?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If you have any query, please do not hesitate to ask me.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks in advance.&lt;/P&gt;&lt;P&gt;Kang.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 01 Feb 2016 12:40:07 GMT</pubDate>
    <dc:creator>daeilkang</dc:creator>
    <dc:date>2016-02-01T12:40:07Z</dc:date>
    <item>
      <title>T2080 cache partition</title>
      <link>https://community.nxp.com/t5/T-Series/T2080-cache-partition/m-p/478944#M628</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear All&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am going to devlop the system by using T2080 and VxWorks 653 3.0 version.&lt;/P&gt;&lt;P&gt;I will use the fsl_t2080_qds evaluation board from freescale.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Question 1&amp;gt;&lt;/P&gt;&lt;P&gt;The L2 cahe of T2080 is shared among foru physical cores.&lt;/P&gt;&lt;P&gt;Is there any way to partition the L2 Cache to each core??&lt;/P&gt;&lt;P&gt;Please let me know how to do that.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Question 2&amp;gt;&lt;/P&gt;&lt;P&gt;There are two memac ports (memac 2 and memac 3) in t2080 QDS board.&lt;/P&gt;&lt;P&gt;I want to test different network configuration with this board.&lt;/P&gt;&lt;P&gt;First, I want to configure that&amp;nbsp; only one core can hanle tow memac ports.&lt;/P&gt;&lt;P&gt;What shall I do this?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Second, I also wanto to configure that first core hansles memac2, and second core handles memac3, respectively.&lt;/P&gt;&lt;P&gt;What shall I do this?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Third, If I want to add another memac port, like memac4.&lt;/P&gt;&lt;P&gt;What shall I do this?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If you have any query, please do not hesitate to ask me.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks in advance.&lt;/P&gt;&lt;P&gt;Kang.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 01 Feb 2016 12:40:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T2080-cache-partition/m-p/478944#M628</guid>
      <dc:creator>daeilkang</dc:creator>
      <dc:date>2016-02-01T12:40:07Z</dc:date>
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    <item>
      <title>Re: T2080 cache partition</title>
      <link>https://community.nxp.com/t5/T-Series/T2080-cache-partition/m-p/478945#M629</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt; 1) Look at the Section 2.12.4 of the e6500 Core Reference Manual:&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="http://cache.nxp.com/files/32bit/doc/ref_manual/E6500RM.pdf?fsrch=1&amp;amp;sr=2&amp;amp;pageNum=1" rel="nofollow"&gt;http://cache.nxp.com/files/32bit/doc/ref_manual/E6500RM.pdf?fsrch=1&amp;amp;sr=2&amp;amp;pageNum=1&lt;/A&gt;&lt;/P&gt;&lt;P&gt;2) It looks like that these questions are specific to VxWorks. If NXP SDK is used, see kernel configuration using kernel menu and .dts file.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Pavel&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 02 Feb 2016 06:01:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T2080-cache-partition/m-p/478945#M629</guid>
      <dc:creator>Pavel</dc:creator>
      <dc:date>2016-02-02T06:01:24Z</dc:date>
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