T-Series中的主题 Re: T2080 ATMU setup for PCIe1

T2080 ATMU setup for PCIe1

scottgerhold — Mon, 23 May 2022 13:46:53 GMT

I have 2 T2080s attached to each other on PCIe. I have 1 setup as the RC and the other setup as the EP. I am only testing traffic (reads/writes) to the EP from the RC. When I run the test for connections between PCIe2 or PCIe4 the test functions correctly and data written to the EP is echoed back correctly on reads from the EP. The test is simply mapping to DRAM on the EP's T2080. So the ATMU registers, LAWs, TLBs are set up correctly.

However, the test fails when using PCIe1. The configuration is exactly the same for all three controller setups. The SW simply is compiled to change the bus from PCIe4 to PCIe1 with appropriate memory changes to the controllers. We have a PCIe analyzer on the bus. We see the writes and reads complete as expected. But the data read back does not represent the data written in the prior step by the RC. When we break in with an emulator from the RC and examine the memory space mapped to the EP DRAM (BAR1) through the PCIe bus, it appears to be a repeating pattern. When I break in to the T2080 EP processor and examine DRAM it is unchanged from the original values written during DRAM init. What is different about PCIe1. I realize that PCIe1 supports SR-IOV, but I do not have that enabled.

Re: T2080 ATMU setup for PCIe1

yipingwang — Fri, 27 May 2022 02:08:38 GMT

Provide the full console logs
PEX analyser dumps

Re: T2080 ATMU setup for PCIe1

scottgerhold — Thu, 02 Jun 2022 15:37:19 GMT

I am not sure what exactly you are asking for with the PEX analyzer dumps. If you are just looking for proof that what I said is true (that reads don’t return what was written, I can show that).

Re: T2080 ATMU setup for PCIe1

scottgerhold — Thu, 02 Jun 2022 15:37:57 GMT

I am not sure what exactly you are asking for with the PEX analyzer dumps. If you are just looking for proof that what I said is true (that reads don’t return what was written, I can show that).

Re: T2080 ATMU setup for PCIe1

yipingwang — Thu, 16 Jun 2022 02:31:57 GMT

I can provide the RC and EP dumps along with the LAW registers. Do you have a specific address range you want for the PCIe interface dumps? Any hidden registers you want (I know they exist as NXP has told us to change a couple in the past). Are you asking for both the normal registers and the PCIe configuration memory space (that is a little harder to get, but I can dump the screen from Lauterbach – which is 98% correct).
[NXP] Yes. We want the dumps for the normal registers and the PCIe configuration space. Do this activity for both RC and EP. You may refer to Table 2-5. CCSR Block Base Address Map from T2080RM for PCIe offset. In addition, the register dump of LAW registers is also required.

I am not sure what exactly you are asking for with the PEX analyzer dumps. If you are just looking for proof that what I said is true (that reads don’t return what was written, I can show that).
[NXP] We need PEX analyzer dumps in the failing scenario, i.e., when reads don’t return the written data. It would be great if you also shared analyzer dumps in the passing case to compare.

Re: T2080 ATMU setup for PCIe1

sophiaanderson — Sun, 26 Jul 2026 07:34:16 GMT

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Re: T2080 ATMU setup for PCIe1

samuelwhite — Sun, 26 Jul 2026 09:55:49 GMT

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Re: T2080 ATMU setup for PCIe1

jameswilson935 — Mon, 27 Jul 2026 05:17:31 GMT

I ran into something similar while working through a PCIe configuration, and checking the documentation carefully made a big difference. I also compared a few hardware reference details with Pinal Assessor Portal while organizing related information for another project. Hopefully your setup goes smoothly, and I'd be interested to hear what ended up resolving the issue. Thanks for bringing up this topic.

Re: T2080 ATMU setup for PCIe1

hannahreed36 — Sat, 01 Aug 2026 05:28:09 GMT

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