T-SeriesのトピックRe: T2081 512MB NOR Flash

T2081 512MB NOR Flash

arumilli — Fri, 22 May 2026 10:42:15 GMT

Hello,

I am currently working on the T2081 NOR flash configuration with two NOR chips connected on the board:

CS0 – 256MB
CS1 – 256MB

As of now, the 256MB NOR flash on CS0 is working correctly.

The configured address range is:

0xE0000000 to 0xEFFFFFFF

For booting, we are currently using the 128MB region:

0xE8000000 to 0xEFFFFFFF

Now, I would like to increase the NOR flash size to 512MB. Could you please let me know what changes are required for this update?

Thanks and Regards,
Ravindra Arumilli

Re: T2081 512MB NOR Flash

Bio_TICFSL — Fri, 22 May 2026 14:35:41 GMT

Hello,

To increase your T2081 IFC NOR space from 256 MB to 512 MB using two 256 MB NOR devices on CS0 and CS1 , the required changes are:

Expand the IFC memory map to cover the full 512 MB window
Program CS0 and CS1 with non-overlapping IFC base/mask settings
Make the LAW window large enough to cover the combined IFC range
Update U-Boot / Linux device tree partitioning to reflect the new map
Keep boot on CS0, because NOR boot uses CS0 as the boot chip-select ,,,,,

The key correction first: for T2081 NOR boot , the available documentation says the valid default NOR map is 0xE8000000 to 0xEFFFFFFF for a 128 MB boot NOR setup, and NXP guidance for 256 MB NOR is to use 0xE0000000 to 0xEFFFFFFF . Since you now want two x 256 MB = 512 MB total , you should not leave the combined map at only 0xE0000000–0xEFFFFFFF, because that range is only 256 MB . The IFC address decode must be expanded so both 256 MB devices fit without overlap

So, To support 512 MB total NOR on T2081 with two 256 MB chips, expand the LAW to 512 MB, keep CS0 and CS1 as separate 256 MB IFC banks with non-overlapping CSPR/AMASK settings, keep boot on CS0, and update U-Boot/TLB/device-tree mappings to the new combined range.

Regards

Re: T2081 512MB NOR Flash

arumilli — Mon, 25 May 2026 09:21:48 GMT

Hello,

Thank you for the clarification regarding the IFC NOR mapping for the T2081.

We plan to use CS0 at:

CS0 : 0xE0000000 – 0xEFFFFFFF (256 MB)

Could you please confirm what the recommended non-overlapping address range should be for CS1 when using the second 256 MB NOR device?

Since the total NOR size becomes 512 MB, we would like to confirm the correct expanded LAW/IFC address map for CS1 and ensure the combined range is valid for boot and runtime access.

Regards
Ravindra Arumilli

Re: T2081 512MB NOR Flash

Bio_TICFSL — Mon, 25 May 2026 14:03:46 GMT

Hello,

Yes —For T2081, with CS0 at 0xE0000000–0xEFFFFFFF, the correct non-overlapping 256 MB CS1 window is 0xF0000000–0xFFFFFFFF, and the resulting 512 MB is valid as two adjacent IFC banks for runtime access, while boot still uses CS0 only.

Regards

Re: T2081 512MB NOR Flash

arumilli — Wed, 03 Jun 2026 13:16:34 GMT

Hello,

Thank you for the information.

The proposed CS1 window 0xF0000000–0xFFFFFFFF is already being used by other interfaces in our design. Therefore, we are unable to assign this address range to IFC CS1.

Could you please advise on an alternative address range that can be used for CS1 without overlapping with existing allocations?

Regards,