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    <title>T-SeriesのトピックRe: Watchdog Timer implementation</title>
    <link>https://community.nxp.com/t5/T-Series/Watchdog-Timer-implementation/m-p/2361654#M5388</link>
    <description>&lt;P&gt;Each core has an internal watchdog timer. Depending on the values programmed in TCR[WRC] and EDBCR0[EDM], four different actions can be taken upon a watchdog timer expiration, including automatic reset of the corresponding core and assertion of RESET_REQ_B.&lt;/P&gt;
&lt;P&gt;For more details, please refer to &lt;A href="https://www.nxp.com/webapp/Download?colCode=T2080RM" target="_blank"&gt;QorIQ T2080 Reference Manual&lt;/A&gt;,&amp;nbsp; Section 7.3.6.1 “Watchdog Timer Expiration Out to Platform.”&lt;/P&gt;
&lt;P&gt;Thanks.&lt;/P&gt;</description>
    <pubDate>Thu, 07 May 2026 07:51:38 GMT</pubDate>
    <dc:creator>June_Lu</dc:creator>
    <dc:date>2026-05-07T07:51:38Z</dc:date>
    <item>
      <title>Watchdog Timer implementation</title>
      <link>https://community.nxp.com/t5/T-Series/Watchdog-Timer-implementation/m-p/2361130#M5382</link>
      <description>&lt;DIV&gt;&lt;P&gt;We are using an NXP QorIQ T2080 processor and want to implement the internal Watchdog Timer.&lt;/P&gt;&lt;P&gt;Please clarify:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;How to enable the internal Watchdog Timer. Any recommended flow?&lt;/LI&gt;&lt;LI&gt;Whether the Watchdog Timer is core-specific or common for the full processor?&lt;/LI&gt;&lt;LI&gt;Does watchdog timeout internally reset the processor, or does it assert any external reset/request pin?&lt;/LI&gt;&lt;/OL&gt;&lt;/DIV&gt;</description>
      <pubDate>Wed, 06 May 2026 10:11:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/Watchdog-Timer-implementation/m-p/2361130#M5382</guid>
      <dc:creator>dheeraj_07</dc:creator>
      <dc:date>2026-05-06T10:11:38Z</dc:date>
    </item>
    <item>
      <title>Re: Watchdog Timer implementation</title>
      <link>https://community.nxp.com/t5/T-Series/Watchdog-Timer-implementation/m-p/2361654#M5388</link>
      <description>&lt;P&gt;Each core has an internal watchdog timer. Depending on the values programmed in TCR[WRC] and EDBCR0[EDM], four different actions can be taken upon a watchdog timer expiration, including automatic reset of the corresponding core and assertion of RESET_REQ_B.&lt;/P&gt;
&lt;P&gt;For more details, please refer to &lt;A href="https://www.nxp.com/webapp/Download?colCode=T2080RM" target="_blank"&gt;QorIQ T2080 Reference Manual&lt;/A&gt;,&amp;nbsp; Section 7.3.6.1 “Watchdog Timer Expiration Out to Platform.”&lt;/P&gt;
&lt;P&gt;Thanks.&lt;/P&gt;</description>
      <pubDate>Thu, 07 May 2026 07:51:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/Watchdog-Timer-implementation/m-p/2361654#M5388</guid>
      <dc:creator>June_Lu</dc:creator>
      <dc:date>2026-05-07T07:51:38Z</dc:date>
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