topic Re: DDR controller DQ mapping register - how to interpret the TRM section 14.4.49 in T-Series

DDR controller DQ mapping register - how to interpret the TRM section 14.4.49

trevorfox — Wed, 29 Jan 2025 23:53:46 GMT

Hi,

I have a custom board that I have received four of. It has a T1042 with attached DDR3L memory, 72 bit data bus.

Three of the four boards has functional DDR, the fourth is intermittent failures when SW loads the DDR. I am trying to use the NXP Codewarrior QCVS DDR validation tool but it is failing initialization, and I recall from another project that due to the data bits being swizzled on some of the byte lanes, the DQ mapping registers (DDR_DDR_DQ_MAP0/1/2/3) have to be properly set.

I cannot figure out how to set these from the TRM, as it is minimal in description.

Any more explanation or example you can provide would be great.

Thank you

Trevor

T1042DQ	Memory DQ
0	24
1	26
2	28
3	27
4	25
5	31
6	30
7	29
8	40
9	46
10	42
11	43
12	47
13	41
14	44
15	25
16	16
17	17
18	23
19	19
20	20
21	18
22	22
23	21
24	48
25	52
26	51
27	50
28	49
29	54
30	53
31	55
32	66
33	69
34	68
35	63
36	62
37	67
38	64
39	65
40	8
41	12
42	10
43	9
44	15
45	14
46	13
47	11
48	0
49	3
50	4
51	2
52	1
53	5
54	6
55	7
56	56
57	57
58	62
59	63
60	60
61	61
62	58
63	59
D1_MECC0	32
D1_MECC1	34
D1_MECC2	35
D1_MECC3	38
D1_MECC4	39
D1_MECC5	36
D1_MECC6	33
D1_MECC7	37

Re: DDR controller DQ mapping register - how to interpret the TRM section 14.4.49

Hector_Villarruel — Tue, 04 Feb 2025 01:13:14 GMT

Hello
@trevorfox

Hope this post finds you well,

Could you please be so kind to provide us with your CodeWarrior logs/screenshot errors?

Could you please also provide us with your CodeWarrior version and your current OS?

We will be aware for your kind reply.

Have a great day.

Best Regards,

Hector Villarruel S

Re: DDR controller DQ mapping register - how to interpret the TRM section 14.4.49

trevorfox — Tue, 04 Feb 2025 23:50:51 GMT

Codewarrior for PA, v10.5.1

QCVS Rev 4.5

Windows 10

I have attached the screenshot of the error. This only happens on one board, the other one seems to work fine.

Re: DDR controller DQ mapping register - how to interpret the TRM section 14.4.49

Hector_Villarruel — Wed, 05 Feb 2025 02:20:27 GMT

Hello @trevorfox

Hope this post finds you well,

We notice that you create a technical support ticket,

We will keep the communication on #00681961

Have a great day.

BR,

Hector Villarruel S

Re: DDR controller DQ mapping register - how to interpret the TRM section 14.4.49

trevorfox — Mon, 10 Feb 2025 23:21:16 GMT

Hi Hector,
I posted on the support case/ticket #00681961 but have not yet heard anything. Do you know of any updates?

Re: DDR controller DQ mapping register - how to interpret the TRM section 14.4.49

Hector_Villarruel — Tue, 11 Feb 2025 02:09:34 GMT

Hello @trevorfox

Hope this post finds you well,

There is an update available on case #00681961

Kindly keep the communication on such case.

Have a great day.

BR,

Hector Villarruel

Re: DDR controller DQ mapping register - how to interpret the TRM section 14.4.49

trevorfox — Mon, 17 Feb 2025 14:50:28 GMT

Hi @Hector_Villarruel Hector,

I have posted a response to your post on the support ticket, 00681961. Do you have any updates?

Trevor

Re: DDR controller DQ mapping register - how to interpret the TRM section 14.4.49

Hector_Villarruel — Tue, 18 Feb 2025 17:30:07 GMT

Hello @trevorfox

Hope this post finds you well,

I have sent you an update from on the ticket #00681961

Kindly keep the communication on #00681961

Thank you for your understanding.

Have a great day.

BR,

Hector Villarruel