T2080 Low power section security violaiton

Ryun — Wed, 05 Feb 2025 06:50:17 GMT

Hello.
I'm trying to apply secure boot through a custom board with a t2080 chip.

There are two main questions I want to ask.

1. CCSR INGR: I followed the document and wrote key values in mirror registers and fused key values by writing 0x00000002 values in 0xfe0e8020.
However, the ITS bit is not enabled in SFP_OSFR.
Is it an error in the fuse process?

2. I am trying to test using SB_EN=1 because ITS bit is not active.
However, SSM_ST of SECMON_HPSR does not change from Check.

Also in SECMON_HPSVSR, it show Low power section security violation.
PGD bit is enabled in LPSR, LPPGDR shows 0x00000000 value.
In the t2080 dataset, it seems that TMP_DETECT_B is 1.8v, is this a problem?
Should this be connected to 3.3v?

Does this power glitch not make my board secure boot?

I look forward to hearing answer. Thank you.
From Ryun

Re: T2080 Low power section security violaiton

June_Lu — Sat, 08 Feb 2025 09:20:57 GMT

For the secure debug, please kindly use your company email and create case in the https://support.nxp.com/s/?language=en_US, then provide NDA to join our Trust Architecture Users Group to get QorIQ Trust Architecture 2.0 User Guide.

For the TMP_DETECT_B, please confirm it follows the AN4804, QorIQ T2080 Design Checklist - Application Note, but anyway, it is supplied by the OVDD(1.8V), I don't think I could accept 3.3V signal.

Thanks

topic Re: T2080 Low power section security violaiton in T-Series

T2080 Low power section security violaiton

Re: T2080 Low power section security violaiton