topic Re: DDR4 initialization issue in T1022 in T-Series

DDR4 initialization issue in T1022

Kernelhacker — Thu, 04 Jul 2024 04:20:44 GMT

In follow up to this post:

https://community.nxp.com/t5/CodeWarrior-for-QorIQ/DDR-single-bit-fault-detected-by-ecc/m-p/1893988/highlight/false

As per advice from nxp team, setup a bareboard project with "attach" launch configuration. The ddr controller register was copied (attached).

But the dump format doesn't match with with register export format from qcvs.

Anyway after comparison and modification imported back the registers. and again started validation.

However the result is same.

Now u-boot is stuck where u-boot is copied from spi flash to ddr. (attached)

Re: DDR4 initialization issue in T1022

Kernelhacker — Mon, 08 Jul 2024 03:54:49 GMT

Dear NXP team,

we are stuck with this problem, please assist.

Re: DDR4 initialization issue in T1022

yipingwang — Mon, 08 Jul 2024 09:30:52 GMT

After creating a QCVS DDR project with reading from SPD method.

In properties panel, please configure "DQ mapping - Controller pins" information according to your DDR design schematics.

The DQ_MAPn registers, provide the mapping information of the DRAM DQ order to the controller. controller uses this information during the initialization when training pattern are send and received. when controller does not have or has the wrong map it is not able to perform initialization of DRAM chips.

Re: DDR4 initialization issue in T1022

Priyanka_Yadav — Thu, 11 Jul 2024 11:05:22 GMT

Please find attached our DDR4 connector and T1022 schematic pages, there is one is to one mapping in our design. Please suggest what should be the setting value for DQ_MAPn registers in this case.

Thanks...

Re: DDR4 initialization issue in T1022

Kernelhacker — Thu, 11 Jul 2024 11:15:01 GMT

As Priyanka said, the mapping from Processor to connector is one is to one.
And from Connector to SDRAM, bit map is as per spd contents Byte 60 to 77. The above dimm is tested and works on some other boards. so the spd bit map must be correct.

Re: DDR4 initialization issue in T1022

yipingwang — Fri, 12 Jul 2024 10:54:09 GMT

Discussing this problem with the AE team.

Re: DDR4 initialization issue in T1022

Kernelhacker — Tue, 16 Jul 2024 12:04:34 GMT

Dear NXP team, please assist.

Re: DDR4 initialization issue in T1022

yipingwang — Wed, 17 Jul 2024 05:42:27 GMT

I didn't get feedback from the AE team, will contact them again.

Re: DDR4 initialization issue in T1022

yipingwang — Fri, 19 Jul 2024 02:14:44 GMT

in QCVS after the SPD configuration is complete, then go to "operational DDR test" and run write-read-compare test. if it fails, then get the full ddr register dump via ccs and send it.

How to get register dump via ccs
This is for debug use only.
1) Open a CCS window (C:\Freescale\CW4NET_xxxxx\Common\CCS\bin\ccs.exe)
2) Physical connection: USB to PC, JTAG to the customer board.
3) SW connection: in the ccs window type:

delete all
config cc cwtap
ccs::config_chain t1040
display ccs::read_mem 0 0x30000 0x8000 4 2 1024
ccs::write_mem 0 0x30000 0x8FB0 4 2 0x10000000
display ccs::read_mem 0 0x30000 0x8000 4 2 1024

Re: DDR4 initialization issue in T1022

Kernelhacker — Fri, 19 Jul 2024 09:30:27 GMT

operational test 'write-read-compare failed (see write-read-compare.png)

Please find attached reg dump (ccs_ddr_dump.txt)

Can you explain why the start address of ddr test is fixed at 0x100000000, and any other address is not allowed. (see write-read-compare-start_address.png and write-read-compare-start_address_err.png)

I think DDR mem is mapped in the lower 2GB space(from 0x0) in u-boot.

Thanks

Debdutta

Re: DDR4 initialization issue in T1022

yipingwang — Thu, 25 Jul 2024 01:53:34 GMT

Please bring the board (that you want to test on the QCVS DDR tool) to uboot prompt. when board working and at uboot prompt, get a CCS register dump as described previously and send the dump log.

How to get register dump via ccs
This is for debug use only.
1) Open a CCS window (C:\Freescale\CW_PA_v10.5.1\PA\ccs\bin\ccs.exe)
2) Physical connection: USB to PC, JTAG to the customer board.
3) SW connection: in the ccs window type:

delete all
config cc cwtap
ccs::config_chain t1040
display ccs::read_mem 0 0x30000 0x8000 4 2 1024
ccs::write_mem 0 0x30000 0x8FB0 4 2 0x10000000
display ccs::read_mem 0 0x30000 0x8000 4 2 1024

Re: DDR4 initialization issue in T1022

Kernelhacker — Thu, 25 Jul 2024 03:53:38 GMT

Hi, the board is not not booting up to u-boot prompt at all. It gets stuck as shown below:

Initializing....using SPD
WARNING: Calling __hwconfig without a buffer and before environment is ready
WARNING: Calling __hwconfig without a buffer and before environment is ready
WARNING: Calling __hwconfig without a buffer and before environment is ready
WARNING: Calling __hwconfig without a buffer and before environment is ready
6 GiB left unmapped
Loading second stage boot loader .................................................................................................

Re: DDR4 initialization issue in T1022

yipingwang — Thu, 25 Jul 2024 04:08:18 GMT

As you mentioned in https://community.nxp.com/t5/CodeWarrior-for-QorIQ/DDR-single-bit-fault-detected-by-ecc/m-p/1893988/highlight/false

>>>No error in ddr initialization in uboot and mtest runs successfully. (see log: uboot_log_mtest.txt)

Please use that configuration.

Re: DDR4 initialization issue in T1022

Kernelhacker — Thu, 25 Jul 2024 04:30:08 GMT

Yes, earlier the board was booting up.
We have not many any configuration change from that.
But now it is not booting up and stuck while downloading uboot to ddr from spi flash.

Re: DDR4 initialization issue in T1022

yipingwang — Thu, 25 Jul 2024 04:40:22 GMT

Is it possible for you to use the original u-boot image to bringing up the target board?

Re: DDR4 initialization issue in T1022

Kernelhacker — Thu, 25 Jul 2024 05:36:24 GMT

While we dont have that u-boot image, we do have the source. So I compiled it and programmed the spi flash with this image.
Unfortunately u-boot is stuck at the same stage.

Re: DDR4 initialization issue in T1022

yipingwang — Thu, 25 Jul 2024 07:39:56 GMT

Discussing your current status with the AE team.

Re: DDR4 initialization issue in T1022

Kernelhacker — Tue, 30 Jul 2024 10:58:53 GMT

Hi NXP team, any updates?

Re: DDR4 initialization issue in T1022

yipingwang — Wed, 31 Jul 2024 02:32:54 GMT

Please refer to the following update from the AE team.

please ask for the following items:

please provide the DIMM part number and its corresponding SPD (in text file).
lower the data rate on the board to 1200MT/s (by changing the RCW), then see if the DDR works. if it still fails at lower data rate, follow the procedure below, customer can check the code and before MEM_EN = 1 is set, change the registers as stated below.

How to bypass DQ mapping

This is for debug use only.

The following steps bypasses the DQ mapping. A debug method to determine if DQ mapping is causing the memory controller initialization failure. Or when customer has violated the DQ bit swap rules in their layout.

1) Set the DDR data rate between 1000MT/s and 1200MT/s.

2) Clear all DQn_MAP registers

3) Set the DDR_SDRAM_CFG_2[DDR_SLOW] = 1

4) Set the DEBUG_2[27] = 1, (i.e. 0x1080F04 = 0x10)

Re: DDR4 initialization issue in T1022

Kernelhacker — Wed, 31 Jul 2024 09:40:35 GMT

1. Micron 8GB: MTA9ADF1G72AZ-3G2E1. PFA (spd.txt) or spd data read from code warrior (spd_code_warrior_dump.txt)

2. On lowering data rate to 1200MT/s by changing RCW[MEM_PLL_RAT] = 00_1100, following error comes while booting:

Initializing....using SPD
DDR clock (MCLK cycle 1667 ps) is slower than DIMM(s) (tCKmax 1600 ps) can support.
WARNING: Calling __hwconfig without a buffer and before environment is ready
WARNING: Calling __hwconfig without a buffer and before environment is ready
WARNING: Calling __hwconfig without a buffer and before environment is ready
WARNING: Calling __hwconfig without a buffer and before environment is ready
Waiting for D_INIT timeout. Memory may not work.
6 GiB left unmapped
Loading second stage boot loader .................................................................................................

I think the RAM doesn't support speed lower than 1333 MT/s (CL = 11). But since system clock is 100 MHz we can't achieve this speed.

However I tried setting data rate to 1300MT/s i.e MEM_PLL_RAT to 00_1101. Doing this does not throw any error but still u-boot fails to load from RAM.

Since we couldn't lower DDR data rate between 1000 MT/s and 1200 MT/s, I didn't procede with the later part of the exercise. Shall we conduct the experiment with DDR data rate at 1300 MT/s?