topic Re: T2080 SRAM in T-Series

T2080 SRAM

ChristinaK — Tue, 20 Feb 2024 08:37:55 GMT

Hi,

What is the On-chip RAM for t2080?

We want to use SRAM for faster operations and we don't intend to use DDR as of now. So how do we access SRAM for the same?

How can we configure SRAM to create stack?

Regards,

Christina

Re: T2080 SRAM

Hector_Villarruel — Sat, 17 Feb 2024 00:11:57 GMT

Hello @ChristinaK

Hope this post finds you well,

This post is to inform you that we acknowledge the receipt of your case,

I Keep working on the solution on this case.

I’ll keep you informed on the process,

Have a great day.

Re: T2080 SRAM

ChristinaK — Tue, 20 Feb 2024 08:49:28 GMT

Hi @Hector_Villarruel ,

Thanks for the response. Kindly provide the steps to configure SRAM.

Regards,

Christina

Re: T2080 SRAM

Hector_Villarruel — Thu, 22 Feb 2024 21:27:35 GMT

Hope this post finds you well,

T2080 has 4 e6500 cores built on Power Architecture®
technology sharing a 2 MB L2 cache & 512 KB CoreNet platform cache (CPC).

If you would like to perform your program without using DDR we highly recommend you to use the 2 MC L2 Cache and the 512 KB CoreNet platform cache for those applications when you will need to use to communicate with the DDR.

T2080 is a big processor, we highly recommend you to use uboot in order to do so or the SDK.

Have a great day.

BR,

Hector

Re: T2080 SRAM

VismaySharma — Wed, 21 Feb 2024 04:19:30 GMT

Hi Hector

I had a similar doubt so basically we should use L2 cache with CPC SRAM? Is it possible to just use CPC SRAM for the stack operation and if so how can we do that?

Thanks in advance

Vismay

Re: T2080 SRAM

Hector_Villarruel — Fri, 23 Feb 2024 19:57:44 GMT

Hope this post finds you well,

The T2080 as I said in my previously reply has 512 KB CoreNet platform cache (CPC).

The SRAM mode registers enable and configure the CPC to be used as SRAM space.

We currently do not have an example to do it, nevertheless here is the process to do it:

You can do it using the CPC_CPCSRCR0 register, this register configures the CPC when it is used as
SRAM.

Please refer to the 8.3.1.1 SRAM Mode Registers located at page 295 of the QorIQ T2080 Reference Manual, Rev. 4, 04/2021

SRAM mode is enabled by CPCSRCR0[SRAMEN], the size of the SRAM address space
is configured by CPCSRCR0[SRAMSZ], and the base address of the SRAM address
space is specified using CPCSRCR0[SRBARL] and CPCSRCR1[SRBARU].

Have a great day.

BR,

Hector