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    <title>topic Re: Verilog code for CPLD T1024RDB in T-Series</title>
    <link>https://community.nxp.com/t5/T-Series/Verilog-code-for-CPLD-T1024RDB/m-p/1760359#M4780</link>
    <description>&lt;P&gt;Thanks June_Lu. The version in the filename is V3.7 but the verilog file inside the zip is V1.0. Is this the latest version?&lt;/P&gt;</description>
    <pubDate>Tue, 21 Nov 2023 04:57:12 GMT</pubDate>
    <dc:creator>jayviva</dc:creator>
    <dc:date>2023-11-21T04:57:12Z</dc:date>
    <item>
      <title>Verilog code for CPLD T1024RDB</title>
      <link>https://community.nxp.com/t5/T-Series/Verilog-code-for-CPLD-T1024RDB/m-p/1759626#M4777</link>
      <description>&lt;P&gt;Hello. I purchased the T1024RDB evaluation board sometime back. I am looking for the CPLD code in order to design a custom board. Where can I find the CPLD code?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Jay&lt;/P&gt;</description>
      <pubDate>Mon, 20 Nov 2023 09:02:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/Verilog-code-for-CPLD-T1024RDB/m-p/1759626#M4777</guid>
      <dc:creator>jayviva</dc:creator>
      <dc:date>2023-11-20T09:02:52Z</dc:date>
    </item>
    <item>
      <title>Re: Verilog code for CPLD T1024RDB</title>
      <link>https://community.nxp.com/t5/T-Series/Verilog-code-for-CPLD-T1024RDB/m-p/1760242#M4779</link>
      <description>&lt;P style="margin: 0in; font-family: Calibri; font-size: 11.0pt;" lang="en-US"&gt;Please see attached.&lt;/P&gt;</description>
      <pubDate>Tue, 21 Nov 2023 02:27:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/Verilog-code-for-CPLD-T1024RDB/m-p/1760242#M4779</guid>
      <dc:creator>June_Lu</dc:creator>
      <dc:date>2023-11-21T02:27:09Z</dc:date>
    </item>
    <item>
      <title>Re: Verilog code for CPLD T1024RDB</title>
      <link>https://community.nxp.com/t5/T-Series/Verilog-code-for-CPLD-T1024RDB/m-p/1760359#M4780</link>
      <description>&lt;P&gt;Thanks June_Lu. The version in the filename is V3.7 but the verilog file inside the zip is V1.0. Is this the latest version?&lt;/P&gt;</description>
      <pubDate>Tue, 21 Nov 2023 04:57:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/Verilog-code-for-CPLD-T1024RDB/m-p/1760359#M4780</guid>
      <dc:creator>jayviva</dc:creator>
      <dc:date>2023-11-21T04:57:12Z</dc:date>
    </item>
    <item>
      <title>Re: Verilog code for CPLD T1024RDB</title>
      <link>https://community.nxp.com/t5/T-Series/Verilog-code-for-CPLD-T1024RDB/m-p/1761373#M4781</link>
      <description>&lt;P style="margin: 0in; font-family: 'Microsoft YaHei'; font-size: 11.0pt;" lang="en-US"&gt;Yes, see the version parameters in the source code.&lt;/P&gt;</description>
      <pubDate>Wed, 22 Nov 2023 01:24:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/Verilog-code-for-CPLD-T1024RDB/m-p/1761373#M4781</guid>
      <dc:creator>June_Lu</dc:creator>
      <dc:date>2023-11-22T01:24:33Z</dc:date>
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