https://community.nxp.com/t5/T-Series/T1024-BOOT-fail/m-p/1487968#M4484 <P><SPAN>Thank you for answering.</SPAN></P> Tue, 12 Jul 2022 08:30:11 GMT kojimiura 2022-07-12T08:30:11Z https://community.nxp.com/t5/T-Series/T1024-BOOT-fail/m-p/1485797#M4482 <P>「4.7.1 Power-On Reset Sequence」excerpt　</P><P>9. If the IFC's NAND Flash interface is configured as the RCW source, the reset block<BR />instructs the IFC to load a boot block from Flash into the internal buffer RAM of the<BR />IFC. Once complete, the reset block proceeds to instruct the Pre-Boot Loader to<BR />begin reading in RCW data. Note that if the IFC NAND Flash interface reports an<BR />ECC error, the device reset sequence is halted indefinitely, waiting for another<BR />PORESET_B or hard reset.</P><P><SPAN>Is this correct in the interpretation that the CPU stops reading the SPI if there is an error in the RCW (SPI read) data?</SPAN>&nbsp;</P> Thu, 07 Jul 2022 01:49:54 GMT https://community.nxp.com/t5/T-Series/T1024-BOOT-fail/m-p/1485797#M4482 kojimiura 2022-07-07T01:49:54Z https://community.nxp.com/t5/T-Series/T1024-BOOT-fail/m-p/1487964#M4483 <P>Yes, correct.</P> Tue, 12 Jul 2022 08:25:49 GMT https://community.nxp.com/t5/T-Series/T1024-BOOT-fail/m-p/1487964#M4483 yipingwang 2022-07-12T08:25:49Z https://community.nxp.com/t5/T-Series/T1024-BOOT-fail/m-p/1487968#M4484 <P><SPAN>Thank you for answering.</SPAN></P> Tue, 12 Jul 2022 08:30:11 GMT https://community.nxp.com/t5/T-Series/T1024-BOOT-fail/m-p/1487968#M4484 kojimiura 2022-07-12T08:30:11Z