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    <title>topic Re: How to inject CPC single-bit ECC error in T-Series</title>
    <link>https://community.nxp.com/t5/T-Series/How-to-inject-CPC-single-bit-ECC-error/m-p/1446868#M4429</link>
    <description>&lt;P&gt;&lt;SPAN&gt;There is no example available, but you can refer to the 'L2 SYSFS parts' in the source file drivers/edac/mpc85xx_edac.c and write injection routine to operate the following registers. &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;13.2.14 CPC error injection low register (CPC_CPCERRINJLO)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;13.2.15 CPC error injection control register (CPC_CPCERRINJCTL)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;13.2.16 CPC capture data high register (CPC_CPCCAPTDATAHI)&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Thu, 21 Apr 2022 02:48:02 GMT</pubDate>
    <dc:creator>yipingwang</dc:creator>
    <dc:date>2022-04-21T02:48:02Z</dc:date>
    <item>
      <title>How to inject CPC single-bit ECC error</title>
      <link>https://community.nxp.com/t5/T-Series/How-to-inject-CPC-single-bit-ECC-error/m-p/1433279#M4406</link>
      <description>&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;P&gt;How to inject CPC single-bit ECC error for T1040QDS?&lt;/P&gt;&lt;P&gt;is there any example available to create a single-bit ECC fault ?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Minghu&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Thu, 24 Mar 2022 08:04:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/How-to-inject-CPC-single-bit-ECC-error/m-p/1433279#M4406</guid>
      <dc:creator>minghu_du</dc:creator>
      <dc:date>2022-03-24T08:04:27Z</dc:date>
    </item>
    <item>
      <title>Re: How to inject CPC single-bit ECC error</title>
      <link>https://community.nxp.com/t5/T-Series/How-to-inject-CPC-single-bit-ECC-error/m-p/1433283#M4407</link>
      <description>&lt;P&gt;I have successfully injected single-bit data ECC error on DDR. The error injection registers of CPC are very similar to DDR's, with some minor differences. But I have never been able to successfully inject single-bit data ECC error on CPC.&lt;/P&gt;</description>
      <pubDate>Thu, 24 Mar 2022 08:12:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/How-to-inject-CPC-single-bit-ECC-error/m-p/1433283#M4407</guid>
      <dc:creator>minghu_du</dc:creator>
      <dc:date>2022-03-24T08:12:49Z</dc:date>
    </item>
    <item>
      <title>Re: How to inject CPC single-bit ECC error</title>
      <link>https://community.nxp.com/t5/T-Series/How-to-inject-CPC-single-bit-ECC-error/m-p/1434617#M4411</link>
      <description>&lt;P&gt;registers for ECC testing: the &lt;SPAN&gt;CPCx_CPCERRINJHI&lt;/SPAN&gt; and &lt;SPAN&gt;CPCx_CPCERRINJLO&lt;/SPAN&gt; define which bits you wish to corrupt,&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;CPCx_CPCERRINJCTL&lt;/SPAN&gt;[&lt;SPAN&gt;TERRIEN&lt;/SPAN&gt;]=1 enables error insertion.&lt;/P&gt;
&lt;P&gt;The test sequence can be as following:&lt;/P&gt;
&lt;P&gt;1) &lt;SPAN&gt;CPCx_CPCERRINJLO&lt;/SPAN&gt;=00000001 (the LSbit of 64-bit word is going to be inverted);&lt;/P&gt;
&lt;P&gt;2) &lt;SPAN&gt;CPCx_CPCERRINJCTL&lt;/SPAN&gt;[&lt;SPAN&gt;TERRIEN&lt;/SPAN&gt;]=1;&lt;/P&gt;
&lt;P&gt;3) to write 0000000000000001 to some location (actually 0000000000000000 will be written due to above steps);&lt;/P&gt;
&lt;P&gt;4) to read the location, result should be 0000000000000001 (LSbit is corrected). &lt;SPAN&gt;CPCx_CPCERRCTL&lt;/SPAN&gt; register should report&amp;nbsp; a &lt;STRONG&gt;single-bit&lt;/STRONG&gt; ECC error.&lt;/P&gt;</description>
      <pubDate>Mon, 28 Mar 2022 07:24:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/How-to-inject-CPC-single-bit-ECC-error/m-p/1434617#M4411</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2022-03-28T07:24:18Z</dc:date>
    </item>
    <item>
      <title>Re: How to inject CPC single-bit ECC error</title>
      <link>https://community.nxp.com/t5/T-Series/How-to-inject-CPC-single-bit-ECC-error/m-p/1437525#M4420</link>
      <description>&lt;P&gt;Hi, Yiping,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks for your reply, I still did not succeed in injecting the ECC error after using your steps&lt;/P&gt;&lt;P&gt;I have some follow-up questions, for the second step you mentioned 2)CPCx_CPCERRINJCTL[&lt;STRONG&gt;TERRIEN&lt;/STRONG&gt;]=1;, shouldn't it be enabling the DERRIEN bit?&lt;/P&gt;&lt;P&gt;And in the third step, I would like to know if it is written to memory via load/store instructions or to cache via data cache operation instructions. Have you tried these steps on the board?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks and Best Regards,&lt;/P&gt;&lt;P&gt;Minghu.&lt;/P&gt;</description>
      <pubDate>Fri, 01 Apr 2022 08:17:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/How-to-inject-CPC-single-bit-ECC-error/m-p/1437525#M4420</guid>
      <dc:creator>minghu_du</dc:creator>
      <dc:date>2022-04-01T08:17:08Z</dc:date>
    </item>
    <item>
      <title>Re: How to inject CPC single-bit ECC error</title>
      <link>https://community.nxp.com/t5/T-Series/How-to-inject-CPC-single-bit-ECC-error/m-p/1446868#M4429</link>
      <description>&lt;P&gt;&lt;SPAN&gt;There is no example available, but you can refer to the 'L2 SYSFS parts' in the source file drivers/edac/mpc85xx_edac.c and write injection routine to operate the following registers. &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;13.2.14 CPC error injection low register (CPC_CPCERRINJLO)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;13.2.15 CPC error injection control register (CPC_CPCERRINJCTL)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;13.2.16 CPC capture data high register (CPC_CPCCAPTDATAHI)&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 21 Apr 2022 02:48:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/How-to-inject-CPC-single-bit-ECC-error/m-p/1446868#M4429</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2022-04-21T02:48:02Z</dc:date>
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