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    <title>T-Series中的主题 Re: 1000Base-KX Mode</title>
    <link>https://community.nxp.com/t5/T-Series/1000Base-KX-Mode/m-p/1372055#M4313</link>
    <description>&lt;P&gt;Well, we are able to read these registers now using Clause 45 approach.&lt;BR /&gt;A reference to DEV_ADDR in the documentation caused the confusion&amp;nbsp; as we thought this is the PHY address.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Tue, 16 Nov 2021 14:06:29 GMT</pubDate>
    <dc:creator>valkir</dc:creator>
    <dc:date>2021-11-16T14:06:29Z</dc:date>
    <item>
      <title>1000Base-KX Mode</title>
      <link>https://community.nxp.com/t5/T-Series/1000Base-KX-Mode/m-p/1371345#M4305</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;/P&gt;&lt;P&gt;On our T2080 board we are trying to configure two backplane Ethernet interfaces in 1000Base-KX mode. We are following the procedure of the Para 19.6.1.2 1000Base-KX from the T2080RM. This seems to be working. However we are getting troubles when we are trying to access 1000Base-KX MDIO devices.&lt;/P&gt;&lt;P&gt;As according to the documentation there are several Clause 45 PHY devices available: 0x03, 0x07 and 0x1d.&lt;/P&gt;&lt;P&gt;However we are not able to access those devices.&lt;/P&gt;&lt;P&gt;The documentation for T2080 (Para 19.5.5 of the RM) states:&lt;/P&gt;&lt;P&gt;&lt;EM&gt;The 1000Base-KX PCS register space is selected when the associated&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;SGMIInCR1[MDEV_PORT] matches the Ethernet MAC port address&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;(MDIO_CTL[PORT_ADDR]) and the device address (MDIO_CTL[DEV_ADDR]) is&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;03h.&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;But if we change default value 0x0 in MDEV_PORT field of the corresponding register SGMIInCR1 to 0x03 we are not getting the expected values by accessing the device with the address 0x3.&lt;/P&gt;&lt;P&gt;What is the right way to access the 1000Base-KX MDIO registers, defined by in Para 19.5.5 - 19.5.7 ?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Configuration used:&lt;BR /&gt;&lt;BR /&gt;SerDes configuration&amp;nbsp; BC-18 from the Table 19-1 with Lanes C and D connected to the backplane in SGMII mode (by RCW) and re configured to 1000Base-KX after reset.&lt;/P&gt;&lt;P&gt;As we understand these lanes are mapped to the SGMII_H and SGMII_G&lt;/P&gt;</description>
      <pubDate>Mon, 15 Nov 2021 12:57:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/1000Base-KX-Mode/m-p/1371345#M4305</guid>
      <dc:creator>valkir</dc:creator>
      <dc:date>2021-11-15T12:57:32Z</dc:date>
    </item>
    <item>
      <title>Re: 1000Base-KX Mode</title>
      <link>https://community.nxp.com/t5/T-Series/1000Base-KX-Mode/m-p/1372055#M4313</link>
      <description>&lt;P&gt;Well, we are able to read these registers now using Clause 45 approach.&lt;BR /&gt;A reference to DEV_ADDR in the documentation caused the confusion&amp;nbsp; as we thought this is the PHY address.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 16 Nov 2021 14:06:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/1000Base-KX-Mode/m-p/1372055#M4313</guid>
      <dc:creator>valkir</dc:creator>
      <dc:date>2021-11-16T14:06:29Z</dc:date>
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