topic Re: Determining T1042 timebase frequency in T-Series

Determining T1042 timebase frequency

nakrachi — Wed, 22 Sep 2021 18:27:20 GMT

Hi Everyone,

We are trying to determine the right frequency at which the timebase is updated.

According to the reference manual the core timebase frequency is calculated as follows :

Timebase clock = (platform_clock/16) / TBCLKDIVR

in our case :

Platform clock is 600 Mhz
RCPM_PCTBCKSELR is 0 -> Core Timebase is clocked with Platform Clock /16
TBCLKDIVR is 0x2 -> 1/8

so our timebase frequency should be : 600/(16*8) = 4.6875 Mhz

but when measuring with the logic analyzer we get a timebase frequency of 50Mhz.

I would like to confirm if I a calculated the right frequency or if I missed something,

thank you

Re: Determining T1042 timebase frequency

ufedor — Thu, 23 Sep 2021 04:02:21 GMT

You wrote:

> when measuring with the logic analyzer we get a timebase frequency of 50Mhz

How exactly you did that?

Re: Determining T1042 timebase frequency

nakrachi — Thu, 23 Sep 2021 08:14:54 GMT

Thanks for the reply,

I did set the decrementer to a value of 50000 ticks

with Auto reload enabled (TCR= 0x0000000000400000)

then in the decrementer exception vector (IVOR10) I toggle a GPIO which I measure with the logic analyzer.

I get a frequency of 1Khz (a period of 1 ms)

which makes me believe I am running at 50 Mhz (50000 * 1Khz)

Re: Determining T1042 timebase frequency

ufedor — Thu, 23 Sep 2021 18:28:33 GMT

DECAR in your case is zero.

Re: Determining T1042 timebase frequency

nakrachi — Thu, 23 Sep 2021 18:40:13 GMT

The only pin available to me was the UART_SOUT which I had to configure as GPIO1[15] by modifying the RCW.

I used the debugger RCW override function to use my new RCW, I figured out that the debugger will set the platform PLL to 4:1 even though my RCW is setting it to be 6:1. meaning that my platform clock is 400 Mhz and not 600 Mhz (SYSCLK is 100Mhz).

which make a little bit more sense, if we consider that platform clock is only divided by TBCLKDIVR, 400Mhz/8 = 50 Mhz

I think that "RCPM_PCTBCKSELR is 0 -> Core Timebase is clocked with Platform Clock /16" statement is not true.

Can you please confirm.

thank you

Re: Determining T1042 timebase frequency

nakrachi — Thu, 23 Sep 2021 18:48:31 GMT

The debugger can't read it (according to core manual "The DECAR contents cannot be read")

but I know that I wrote the right value and I am getting decremented exceptions at a fixed interval.

Re: Determining T1042 timebase frequency

ufedor — Fri, 24 Sep 2021 04:27:18 GMT

Please show using Trace32 values of:

RCPM_PCTBCKSELR

RCPM_TBCLKDIVR

Re: Determining T1042 timebase frequency

nakrachi — Fri, 24 Sep 2021 08:56:50 GMT

Here is a screenshot

Re: Determining T1042 timebase frequency

ufedor — Fri, 24 Sep 2021 09:02:33 GMT

What is SYSCLK frequency?

Please provide U-Boot booting log.

Re: Determining T1042 timebase frequency

nakrachi — Fri, 24 Sep 2021 09:04:47 GMT

The system frequency is 100MHz

here is the u-boot log

Re: Determining T1042 timebase frequency

ufedor — Fri, 24 Sep 2021 09:15:45 GMT

600/50=12

I have no idea how such ratio can be obtained.

Re: Determining T1042 timebase frequency

nakrachi — Fri, 24 Sep 2021 09:19:34 GMT

Thanks for the quick replies,

as I mentioned in an earlier comment, I found out that using the temporary RCW has set my PLL ration to 4:1 so I was running at 400Mhz when I got 50Mhz.

Now after setting back the platform clock to 600Mhz I measure a time base frequency of 75Mhz. (600/8)

which makes me believe that the user manual is wrong

Re: Determining T1042 timebase frequency

ufedor — Fri, 24 Sep 2021 09:30:01 GMT

Please combine all consistent experimental data into single Word or PDF document.

Re: Determining T1042 timebase frequency

nakrachi — Fri, 24 Sep 2021 09:39:13 GMT

just making sure, you want me to describe the issue with relevant data/screenshots and post it here ?

thanks

Re: Determining T1042 timebase frequency

ufedor — Fri, 24 Sep 2021 09:45:24 GMT

Yes, please.

Re: Determining T1042 timebase frequency

nakrachi — Mon, 27 Sep 2021 09:50:32 GMT

@ufedor please fin attached the requested document.

Thanks

Re: Determining T1042 timebase frequency

nakrachi — Mon, 04 Oct 2021 13:53:43 GMT

Hi @ufedor , just following up on this.

thanks

Re: Determining T1042 timebase frequency

ufedor — Fri, 08 Oct 2021 09:57:49 GMT

Your understanding is correct.

Time base frequency = (Platform clock )/RCPM_TBCLKDIVR When RCPM_PCTBCKSELR [PCTBCKSELn] = 0, Core Timebase is clocked with Platform Clock/ RCPM_TBCLKDIVR [tbclkdiv].

It is recommended to have the default value of RCPM_TBCLKDIVR [tbclkdiv], i.e., 0x00 : 1/16. This field should not be modified by customer as all the testing are done with Timebase clock divider configuration = 1/16.

Comment is added in T1042RM.

Re: Determining T1042 timebase frequency

nakrachi — Wed, 13 Oct 2021 14:42:56 GMT

Thank you,

But then we have another problem, the erratum A-010651 states that the workaround is changing the RCPM_TBCLKDIVR [tbclkdiv], to 0x08 : 1/32.

but you mentioned we should not change it. how can we workaround this errata then ?

thanks