topic Re: All HDLC related registers are having value as 0 in T-Series

All HDLC related registers are having value as 0

suchitasharma — Fri, 19 Feb 2021 04:55:39 GMT

Hi,

We are using T1040 based board, and testing FSL UCC HDLC driver. When we are trying to read the register values related to fast protocol, all are showing 0. But according to data sheet, there should be some value in the registers.

This is the log of the dump:

ucc_hdlc ffe142000.ucc: Dumpinig UCC 0 Registers
UCC0 Fast registers:
Base address: 0x8000080088b0a000
gumr : addr=0x8000080088b0a000, val=0x00000000
upsmr : addr=0x8000080088b0a004, val=0x00000000
utodr : addr=0x8000080088b0a008, val=0x0000
udsr : addr=0x8000080088b0a00c, val=0x0000
ucce : addr=0x8000080088b0a010, val=0x00000000
uccm : addr=0x8000080088b0a014, val=0x00000000
uccs : addr=0x8000080088b0a018, val=0x00
urfb : addr=0x8000080088b0a020, val=0x00000000
urfs : addr=0x8000080088b0a024, val=0x0000
urfet : addr=0x8000080088b0a028, val=0x0000
urfset: addr=0x8000080088b0a02a, val=0x0000
utfb : addr=0x8000080088b0a02c, val=0x00000000
utfs : addr=0x8000080088b0a030, val=0x0000
utfet : addr=0x8000080088b0a034, val=0x0000
utftt : addr=0x8000080088b0a038, val=0x0000
utpt : addr=0x8000080088b0a03c, val=0x0000
urtry : addr=0x8000080088b0a040, val=0x00000000
guemr : addr=0x8000080088b0a090, val=0x00
ucc_hdlc ffe142000.ucc: Dumping UCC 0 Parameter RAM
ucc_hdlc ffe142000.ucc: rbase = 0x0
ucc_hdlc ffe142000.ucc: rbptr = 0x0
ucc_hdlc ffe142000.ucc: mrblr = 0x0
ucc_hdlc ffe142000.ucc: rbdlen = 0x0
ucc_hdlc ffe142000.ucc: rbdstat = 0x0
ucc_hdlc ffe142000.ucc: rstate = 0x0
ucc_hdlc ffe142000.ucc: rdptr = 0x0
ucc_hdlc ffe142000.ucc: riptr = 0x0
ucc_hdlc ffe142000.ucc: tbase = 0x0
ucc_hdlc ffe142000.ucc: tbptr = 0x0
ucc_hdlc ffe142000.ucc: tbdlen = 0x0
ucc_hdlc ffe142000.ucc: tbdstat = 0x0
ucc_hdlc ffe142000.ucc: tstate = 0x0
ucc_hdlc ffe142000.ucc: tdptr = 0x0
ucc_hdlc ffe142000.ucc: tiptr = 0x0
ucc_hdlc ffe142000.ucc: rcrc = 0x0
ucc_hdlc ffe142000.ucc: tcrc = 0x0
ucc_hdlc ffe142000.ucc: c_mask = 0x0
ucc_hdlc ffe142000.ucc: c_pers = 0x0
ucc_hdlc ffe142000.ucc: disfc = 0x0
ucc_hdlc ffe142000.ucc: crcec = 0x0

And also we are unable to write on these registers. For eg, GUMR reg is having R/W access but we are unable to write using devmem on linux and also on uboot.

Can u please suggest what can be done to resolve this issue.

Re: All HDLC related registers are having value as 0

r8070z — Wed, 24 Feb 2021 10:53:36 GMT

What tool did you use to get the dump? How you read and write registers?

Re: All HDLC related registers are having value as 0

suchitasharma — Thu, 25 Feb 2021 05:51:25 GMT

We did not use any tool to get the dump. We enabled the dump functions written in the FSL UCC HDLC driver to get the dump of the registers.

For reading and writing of the registers on Linux we are using devmem.

To read and write on uboot we are using mm and md.

And inside the driver iowrite32be and ioread32be functions are used for writing and reading the registers. But the changes done using these functions are also not getting reflected in the register value.

Re: All HDLC related registers are having value as 0

r8070z — Fri, 26 Feb 2021 11:05:04 GMT

Unfortunately I can say nothing for Linux driver. I from T1040 hardware support. I think there is software problem (at least UCC GUMR cannot be zero). What did you get under U-boot? Did you check CCSSBAR content inder U-boot? CCSRBAR always points to itself.

Re: All HDLC related registers are having value as 0

suchitasharma — Mon, 01 Mar 2021 10:32:49 GMT

We have checked the GUMR and other HDLC related registers under uboot, all are having value 0. Since we are not configuring these registers on uboot, we are assuming they will be having default value which is 0.

And we have checked CCSRBAR register also, it is pointing to itself.

Re: All HDLC related registers are having value as 0

r8070z — Wed, 03 Mar 2021 07:28:35 GMT

Please let us know the CCSRBAR regiser value and UCC registers dump you see under U-boot.

Re: All HDLC related registers are having value as 0

suchitasharma — Thu, 04 Mar 2021 04:14:06 GMT

There was an issue with IRAM code in our board. We are able to see values in all the registers now. Then we enabled internal loopback, and the data was getting transmitted. But we are unable to send data outside the processor. We have configured TxCLK as CLK9 and RxCLK as CLK12 and shorted both the signals.

Please find the attached image which has the clock signal description.

Please suggest if we can do something to send data outside the processor.

Re: All HDLC related registers are having value as 0

r8070z — Fri, 05 Mar 2021 12:31:35 GMT

Please check the RCW for HDLC pins settings (RCW[QE_TDMA, QE_TDMB] RCW[UC1_CTSB_CDB_SEL, UC3_CTSB_CDB_SEL])