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    <title>topic Re: read - write between DDR and T1024 in T-Series</title>
    <link>https://community.nxp.com/t5/T-Series/read-write-between-DDR-and-T1024/m-p/1229208#M3970</link>
    <description>&lt;P&gt;NXP supports only CodeWarrior IDE for development and debugging.&lt;/P&gt;
&lt;P&gt;Please refer to the attached T1024RDB initialization script as example.&lt;/P&gt;</description>
    <pubDate>Wed, 10 Feb 2021 09:30:58 GMT</pubDate>
    <dc:creator>ufedor</dc:creator>
    <dc:date>2021-02-10T09:30:58Z</dc:date>
    <item>
      <title>read - write between DDR and T1024</title>
      <link>https://community.nxp.com/t5/T-Series/read-write-between-DDR-and-T1024/m-p/1228717#M3968</link>
      <description>&lt;P&gt;Hi All,&lt;/P&gt;&lt;P&gt;I do not know how to communicate between DDR to T1024, could you support me? Thank you for your consideration.&lt;/P&gt;&lt;P&gt;The memory map is like that:&lt;/P&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;EM&gt;Memory map on T1024RDB&lt;/EM&gt;&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;EM&gt;----------------------&lt;/EM&gt;&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;EM&gt;Start Address End Address Description Size&lt;/EM&gt;&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;EM&gt;0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB&lt;/EM&gt;&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;EM&gt;0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB&lt;/EM&gt;&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;EM&gt;0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB&lt;/EM&gt;&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;EM&gt;0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB&lt;/EM&gt;&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;EM&gt;0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB&lt;/EM&gt;&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;EM&gt;0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB&lt;/EM&gt;&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;EM&gt;0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB&lt;/EM&gt;&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;EM&gt;0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB&lt;/EM&gt;&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;EM&gt;0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB&lt;/EM&gt;&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;EM&gt;0xF_0000_0000 0xF_003F_FFFF DCSR 4MB&lt;/EM&gt;&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;EM&gt;0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB&lt;/EM&gt;&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;EM&gt;0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB&lt;/EM&gt;&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;EM&gt;0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB&lt;/EM&gt;&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;EM&gt;0x0_0000_0000 0x0_ffff_ffff DDR 4Gb&lt;/EM&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;I thought that, I can assign an address to a pointer which defined in the main program, the address is from the range of&amp;nbsp;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;EM&gt;0x0_0000_0000 0x0_ffff_ffff DDR 4Gb&lt;/EM&gt;&lt;/FONT&gt; and when I start to write and read this address, I can use the ddr directly. Is it correct?&lt;/P&gt;&lt;P&gt;I have done this method in pc, i had a segmentation fault error. Could you guide me?&lt;/P&gt;&lt;P&gt;Thank you for your consideration.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 09 Feb 2021 10:40:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/read-write-between-DDR-and-T1024/m-p/1228717#M3968</guid>
      <dc:creator>emras</dc:creator>
      <dc:date>2021-02-09T10:40:23Z</dc:date>
    </item>
    <item>
      <title>Re: read - write between DDR and T1024</title>
      <link>https://community.nxp.com/t5/T-Series/read-write-between-DDR-and-T1024/m-p/1229208#M3970</link>
      <description>&lt;P&gt;NXP supports only CodeWarrior IDE for development and debugging.&lt;/P&gt;
&lt;P&gt;Please refer to the attached T1024RDB initialization script as example.&lt;/P&gt;</description>
      <pubDate>Wed, 10 Feb 2021 09:30:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/read-write-between-DDR-and-T1024/m-p/1229208#M3970</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2021-02-10T09:30:58Z</dc:date>
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