T1024 Single Clock mode

giacomo_gaspari — Wed, 10 Jun 2020 12:42:23 GMT

Hi,

Actually we are using the CPU with the following clock fed but we have problems with SerDes locking at startup:

- 100MHz 1.8V DC-LVDS clock to DIFF_SYSCLK_P/N inputs;

- 100MHz 2.5V AC-LVPECL clock to SD1_REF_CLK1_P/N inputs;

- 100MHz 2.5V AC-LVPECL clock to SD1_REF_CLK2_P/N inputs;

Considerations:

In 4.7.7.1.1 from RM is written that:

In this mode, single onboard oscillator can provide the reference clock (100MHz) to the
following PLLs:
• Platform PLL
• Core PLLs
• USB PLL
• DDR PLL
• SerDes PLLs

In fig. 4-3 "single oscillator mode", from RM: the 2x SerDes PLL are feed externally;

In 4.1.1, datasheet it's written:

When using Single Oscillator Source clocking mode, a single onboard oscillator can provide the reference clock (100 MHz) to all the PLLs (that is, Platform PLL, CoreCluster PLLs, DDR PLL, USB PLL and SerDes PLLs).

In table 138, datasheet it's written:

"Single Oscillator Source" Reference clock mode supports differential reference clock pair frequency of 100 MHz.

In 4.1.7, datasheet it's written:

The clock ratio between each of the two SerDes PLLs and their respective externally supplied SD1_REF_CLKn_P/SD1_REF_CLKn_N inputs is determined by [...]

Questions:

- is it true that SerDes PLL1/2 could be feed from ONLY one reference 100MHz differential clock (DIFF_SYSCLK_P/N) in "Single Oscillator Source clocking mode"?

- How can we enable "Single Oscillator Source clocking mode"?

Thank you.

Giacomo

Re: T1024 Single Clock mode

Bulat — Wed, 10 Jun 2020 16:03:39 GMT

Figure 4-3 of the manual is correct, Serdes reference clocks should be provided externally. "Single oscillator source" means that one clock source with fanout outputs can be used as a clock source as shown in the figure. The clock at DIFF_SYSCLK pins can not be used to clock Serdes internally.

Regards,

Bulat

Re: T1024 Single Clock mode

giacomo_gaspari — Thu, 11 Jun 2020 06:13:24 GMT

Thank you Bulat.

Cheers!

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