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    <title>T-Series中的主题 T2080 CGA_PLL1_RAT</title>
    <link>https://community.nxp.com/t5/T-Series/T2080-CGA-PLL1-RAT/m-p/1072184#M3697</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We are running SYSCLK at 100MHz. We are using PLL1 to drive the FMAN. We use Processor Expert to create the RCW. In the past I have been able to set CGA_PLL1_RAT to 7:1. But now it appears I cannot set it lower than 8:1. Did PE change to limit the value? The reference manual states 5:1 is allowed, but states look elsewhere (datasheet is assumed) to determine limitations.&lt;/P&gt;&lt;P&gt;In the datasheet, Table 121 discusses PLL frequencies. I may have missed the limitation there in the past as I assume it was for the Core frequency, does that require the CGA_PLL1 and CGA_PLL2 to meet a minimum of 1000MHz?&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 06 Aug 2020 16:50:57 GMT</pubDate>
    <dc:creator>scottgerhold</dc:creator>
    <dc:date>2020-08-06T16:50:57Z</dc:date>
    <item>
      <title>T2080 CGA_PLL1_RAT</title>
      <link>https://community.nxp.com/t5/T-Series/T2080-CGA-PLL1-RAT/m-p/1072184#M3697</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We are running SYSCLK at 100MHz. We are using PLL1 to drive the FMAN. We use Processor Expert to create the RCW. In the past I have been able to set CGA_PLL1_RAT to 7:1. But now it appears I cannot set it lower than 8:1. Did PE change to limit the value? The reference manual states 5:1 is allowed, but states look elsewhere (datasheet is assumed) to determine limitations.&lt;/P&gt;&lt;P&gt;In the datasheet, Table 121 discusses PLL frequencies. I may have missed the limitation there in the past as I assume it was for the Core frequency, does that require the CGA_PLL1 and CGA_PLL2 to meet a minimum of 1000MHz?&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 06 Aug 2020 16:50:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T2080-CGA-PLL1-RAT/m-p/1072184#M3697</guid>
      <dc:creator>scottgerhold</dc:creator>
      <dc:date>2020-08-06T16:50:57Z</dc:date>
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    <item>
      <title>Re: T2080 CGA_PLL1_RAT</title>
      <link>https://community.nxp.com/t5/T-Series/T2080-CGA-PLL1-RAT/m-p/1072185#M3698</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;gt; does that require the CGA_PLL1 and CGA_PLL2 to meet a minimum of 1000MHz?&amp;nbsp;&lt;/P&gt;&lt;P&gt;Yes.&lt;/P&gt;&lt;P&gt;The Data Sheet requirements must be fulfilled - else normal processor operation is not guaranteed.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 07 Aug 2020 02:40:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T2080-CGA-PLL1-RAT/m-p/1072185#M3698</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2020-08-07T02:40:23Z</dc:date>
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