topic Re: T1020 DDR Configuration in T-Series https://community.nxp.com/t5/T-Series/T1020-DDR-Configuration/m-p/1047549#M3617 <HTML><HEAD></HEAD><BODY><P>References:</P><P>1) <A href="https://community.nxp.com/docs/DOC-330466">Configuring DDR in U-Boot using QCVS</A>&nbsp;</P><P>2) <A _jive_internal="true" class="link-titled" href="https://community.nxp.com/message/907917?commentID=907917#comment-907917" title="https://community.nxp.com/message/907917?commentID=907917#comment-907917">https://community.nxp.com/message/907917?commentID=907917#comment-907917</A>&nbsp;</P></BODY></HTML> Thu, 16 Jul 2020 16:40:36 GMT ufedor 2020-07-16T16:40:36Z T1020 DDR Configuration https://community.nxp.com/t5/T-Series/T1020-DDR-Configuration/m-p/1047548#M3616 <HTML><HEAD></HEAD><BODY><P>Using QCVS document I'm able to do DDR validation. As of now I'm using T1040D4RDB as reference for making DDR changes which is in board/freescale/t104xrdb/ddr.c file. Since T1040D4RDB uses SPD for DDR configuration, I'm getting errors if I directly add generated C code from QCVS tool to the ddr.c file. Pls help me as I'm new into NXP processors</P></BODY></HTML> Wed, 15 Jul 2020 11:53:47 GMT https://community.nxp.com/t5/T-Series/T1020-DDR-Configuration/m-p/1047548#M3616 chetan140 2020-07-15T11:53:47Z Re: T1020 DDR Configuration https://community.nxp.com/t5/T-Series/T1020-DDR-Configuration/m-p/1047549#M3617 <HTML><HEAD></HEAD><BODY><P>References:</P><P>1) <A href="https://community.nxp.com/docs/DOC-330466">Configuring DDR in U-Boot using QCVS</A>&nbsp;</P><P>2) <A _jive_internal="true" class="link-titled" href="https://community.nxp.com/message/907917?commentID=907917#comment-907917" title="https://community.nxp.com/message/907917?commentID=907917#comment-907917">https://community.nxp.com/message/907917?commentID=907917#comment-907917</A>&nbsp;</P></BODY></HTML> Thu, 16 Jul 2020 16:40:36 GMT https://community.nxp.com/t5/T-Series/T1020-DDR-Configuration/m-p/1047549#M3617 ufedor 2020-07-16T16:40:36Z