T1022 Clock Sequence

jack_mcculloch — Wed, 08 Jan 2020 13:13:45 GMT

Hi,

We are designing a custom board with a T1022 processor and would like to know if the there are any power-on sequencing requirements for the clocks?

Do all power rails need to be valid before clocks are enabled?

Is there minimum time the clocks need to be valid before PORESET_B is lifted?

Re: T1022 Clock Sequence

Bulat — Thu, 09 Jan 2020 03:34:05 GMT

SYSCLK can be applied alone with OVDD/O1VDD supplies.
We do not specify "minimum time the clocks need to be valid before PORESET_B".
Minimum PORESET assertion time is 1ms, use it as a 'clock valid' setup as well.

Regards,

Bulat

T-Series中的主题 T1022 Clock Sequence

T1022 Clock Sequence

Re: T1022 Clock Sequence