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    <title>topic Re: Displaying CPC Content in T-Series</title>
    <link>https://community.nxp.com/t5/T-Series/Displaying-CPC-Content/m-p/981975#M3363</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thank you Alexander. I will try the methods for CPC.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sat, 08 Feb 2020 20:20:18 GMT</pubDate>
    <dc:creator>burakorcun_ozka</dc:creator>
    <dc:date>2020-02-08T20:20:18Z</dc:date>
    <item>
      <title>Displaying CPC Content</title>
      <link>https://community.nxp.com/t5/T-Series/Displaying-CPC-Content/m-p/981973#M3361</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello everybody,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm working on CCF (corenet coherency fabric) and CPC (corenet platform cache, or L3 cache) in T1042D4RDB. I studied how CCF works and uses CPC for performance about RAM I/O operations. At this point, i need to display CPC content when data is written to RAM, because i want to test Write-Back and Write-Through policies, also want to know about what happened when the cache is disabled, invalidated and flushed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is there any way to display CPC content?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks in advanced.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 04 Feb 2020 14:12:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/Displaying-CPC-Content/m-p/981973#M3361</guid>
      <dc:creator>burakorcun_ozka</dc:creator>
      <dc:date>2020-02-04T14:12:01Z</dc:date>
    </item>
    <item>
      <title>Re: Displaying CPC Content</title>
      <link>https://community.nxp.com/t5/T-Series/Displaying-CPC-Content/m-p/981974#M3362</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;There is no way to read the contents of CPC, when this device is configured as L3 cache. CPC device may be configured as SRAM, in this case&amp;nbsp;you can read its contents just as common RAM, but when the device is configured in L3 cache mode, this is not possible. To understand the difference between Write-Back anf Write-Through, I recommend using an indirect method - by measuring write times in various write modes (linear write, random write with step higher than cache line size, and etc).&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 06 Feb 2020 21:03:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/Displaying-CPC-Content/m-p/981974#M3362</guid>
      <dc:creator>alexander_yakov</dc:creator>
      <dc:date>2020-02-06T21:03:15Z</dc:date>
    </item>
    <item>
      <title>Re: Displaying CPC Content</title>
      <link>https://community.nxp.com/t5/T-Series/Displaying-CPC-Content/m-p/981975#M3363</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thank you Alexander. I will try the methods for CPC.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 08 Feb 2020 20:20:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/Displaying-CPC-Content/m-p/981975#M3363</guid>
      <dc:creator>burakorcun_ozka</dc:creator>
      <dc:date>2020-02-08T20:20:18Z</dc:date>
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