topic Re: Memory Write or Read 64 bytes access Issue. in T-Series

Memory Write or Read 64 bytes access Issue.

kimpilyeon — Thu, 16 May 2019 02:12:10 GMT

Hi.

I use to T2080 CPU.

development environment is 32 bit, UP.

CS1 is setting VME bus system.

write access function is below.

*(unsigned short *)(vmeVt + DOM01A +0x8) = 0x0101;

As above function, I need to only 2-bytes access.

but, CPU is access read 64 bytes and write 64 bytes.

because cache line size = 64 bytes?

IFC setting value is ..

WRITEADR(r6, r7, T4_IFC_CSPR1_EXT, 0x00000000)
WRITEADR(r6, r7, T4_IFC_FTIM0_CS1, 0xe00e000e)
WRITEADR(r6, r7, T4_IFC_FTIM1_CS1, 0x0E001F00)
WRITEADR(r6, r7, T4_IFC_FTIM2_CS1, 0x0E00001F)
WRITEADR(r6, r7, T4_IFC_FTIM3_CS1, 0x00000000)
WRITEADR(r6, r7, T4_IFC_CSPR1, (VMEBUS_ADRS | 0x0105))
WRITEADR(r6, r7, T4_IFC_AMASK1, ~(VMEBUS_SIZE - 1))
WRITEADR(r6, r7, T4_IFC_CSOR1, 0x400c000c)

TLB setting value is below.

addis r4, 0, 0x1009 /* TLBSEL = TLB1(CAM) , ESEL = 0 */
addis r5, 0, HI(_MMU_TLB_VALID | _MMU_TLB_IPROT)
ori r5, r5, _MMU_TLB_SZ_16M /* TS = 0, TSIZE = 16 MByte page size*/
addis r6, 0, HI(VMEBUS_ADRS) /* EPN */
ori r6, r6, _MMU_TLB_ATTR_G <=== write back setting
addis r7, 0, HI(VMEBUS_ADRS) /* RPN */
ori r7, r7, 0x0015 /* Supervisor XWR*/
li r8, 0x0

I want to know 2-bytes access method. about read and write access.

Re: Memory Write or Read 64 bytes access Issue.

Bulat — Thu, 16 May 2019 04:15:56 GMT

Yes, the core always reads/writes burst lines (64 bytes) when accesses cacheable memory region. You need to change TLB settings and set VME address space as cache-Inhibit and Guarded for proper operations.

Regards,

Bulat

Re: Memory Write or Read 64 bytes access Issue.

kimpilyeon — Thu, 16 May 2019 07:34:31 GMT

Thanks for your help.

I was trying TLB setting cache-Inhibit and Guarded for proper operations. like below.

#define MMU_UNCACHED (_MMU_TLB_ATTR_I | \
_MMU_TLB_ATTR_G)

#define MMU_IO_ACCESS MMU_UNCACHED /* WIMGE bits for IO */

addis r4, 0, 0x1009 /* TLBSEL = TLB1(CAM) , ESEL = 0 */
addis r5, 0, HI(_MMU_TLB_VALID | _MMU_TLB_IPROT)
ori r5, r5, _MMU_TLB_SZ_16M /* TS = 0, TSIZE = 16 MByte page size*/
addis r6, 0, HI(VMEBUS_ADRS) /* EPN */
ori r6, r6, MMU_IO_ACCESS /*MMU_ROM_ACCESS*/
addis r7, 0, HI(VMEBUS_ADRS) /* RPN */
ori r7, r7, 0x0015 /* Supervisor XWR*/
li r8, 0x0

But, write access operation is same before.

hmm.... What another point that needed confirm?

help me.

Re: Memory Write or Read 64 bytes access Issue.

Bulat — Fri, 17 May 2019 04:22:57 GMT

It can mean that cache is still enabled for VME memory. Check you settings once again. Use a debugger for that.

Regards,

Bulat

Re: Memory Write or Read 64 bytes access Issue.

kimpilyeon — Fri, 17 May 2019 08:27:24 GMT

you're right.

It was enabled cache at os booting.

I was used pmapGlobalMap() function for VME memory initialization.

appreciate your help and support.

Best Regards.