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    <title>T-SeriesのトピックRe: PCIe1 issue on T4160RDB-64B</title>
    <link>https://community.nxp.com/t5/T-Series/PCIe1-issue-on-T4160RDB-64B/m-p/854566#M2890</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Ufedor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Serdes1 Frequency -&amp;nbsp; 100MHz&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Serdes2 Frequency - 156.25MHz&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Serdes3 Frequency - 100MHz&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Serdes4 Frequency - 100MHZ&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;EP device is PCI switch&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Regards, VinothS&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 14 Mar 2019 13:27:50 GMT</pubDate>
    <dc:creator>vinothkumars</dc:creator>
    <dc:date>2019-03-14T13:27:50Z</dc:date>
    <item>
      <title>PCIe1 issue on T4160RDB-64B</title>
      <link>https://community.nxp.com/t5/T-Series/PCIe1-issue-on-T4160RDB-64B/m-p/854558#M2882</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear&amp;nbsp; NXP friends,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am working PCI interface on T4160RDB-64B machine.&amp;nbsp; I got no link for PCIe1 and I checked everything in RCW.&lt;/P&gt;&lt;P&gt;PLL1 only we used and PLL2 not used&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Using SERDES1 Protocol: 27 (0x1b)&lt;BR /&gt;Using SERDES2 Protocol: 55 (0x37)&lt;BR /&gt;&lt;STRONG&gt;Using SERDES3 Protocol: 5 (0x5)&lt;/STRONG&gt;&lt;BR /&gt;Using SERDES4 Protocol: 9 (0x9)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;PCIe1: Root Complex, no link, regs @ 0xfe240000&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;PCIe1: Bus 00 - 00&lt;/STRONG&gt;&lt;BR /&gt;PCIe2: disabled&lt;BR /&gt;PCIe3: disabled&lt;BR /&gt;PCIe4: Root Complex, x1 gen1, regs @ 0xfe270000&lt;BR /&gt; 02:00.0 - 126f:0750 - Display controller&lt;BR /&gt;PCIe4: Bus 01 - 02&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;what could be the issue? need to done any configuration in u-boot side.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards, VinothS&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 13 Mar 2019 12:28:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/PCIe1-issue-on-T4160RDB-64B/m-p/854558#M2882</guid>
      <dc:creator>vinothkumars</dc:creator>
      <dc:date>2019-03-13T12:28:15Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe1 issue on T460RDB-64B</title>
      <link>https://community.nxp.com/t5/T-Series/PCIe1-issue-on-T4160RDB-64B/m-p/854559#M2883</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;1) Please provide as text attachment complete U-Boot booting log&lt;/P&gt;&lt;P&gt;2) Which EP device is used?&lt;/P&gt;&lt;P&gt;3) Into which RDB slot it is installed?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 13 Mar 2019 13:04:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/PCIe1-issue-on-T4160RDB-64B/m-p/854559#M2883</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2019-03-13T13:04:25Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe1 issue on T460RDB-64B</title>
      <link>https://community.nxp.com/t5/T-Series/PCIe1-issue-on-T4160RDB-64B/m-p/854560#M2884</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Ufedor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for your reply, and also I attached the log for your reference.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards, VinothS&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 14 Mar 2019 04:06:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/PCIe1-issue-on-T4160RDB-64B/m-p/854560#M2884</guid>
      <dc:creator>vinothkumars</dc:creator>
      <dc:date>2019-03-14T04:06:55Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe1 issue on T460RDB-64B</title>
      <link>https://community.nxp.com/t5/T-Series/PCIe1-issue-on-T4160RDB-64B/m-p/854561#M2885</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Why in the provided log:&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: courier new, courier, monospace;"&gt;Board: T4160RDB, Board rev: &lt;SPAN style="color: #ff0000;"&gt;&lt;STRONG&gt;0x00&lt;/STRONG&gt;&lt;/SPAN&gt; CPLD ver: &lt;SPAN style="color: #ff0000;"&gt;&lt;STRONG&gt;0x0000&lt;/STRONG&gt;&lt;/SPAN&gt;, vBank: 0&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;What is this "T4160RDB"?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 14 Mar 2019 04:23:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/PCIe1-issue-on-T4160RDB-64B/m-p/854561#M2885</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2019-03-14T04:23:50Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe1 issue on T460RDB-64B</title>
      <link>https://community.nxp.com/t5/T-Series/PCIe1-issue-on-T4160RDB-64B/m-p/854562#M2886</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Ufedor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Our board is&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;T4160RDB&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;CPLD is current bank and board revision is 0&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Regards, VinothS&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 14 Mar 2019 05:15:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/PCIe1-issue-on-T4160RDB-64B/m-p/854562#M2886</guid>
      <dc:creator>vinothkumars</dc:creator>
      <dc:date>2019-03-14T05:15:52Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe1 issue on T460RDB-64B</title>
      <link>https://community.nxp.com/t5/T-Series/PCIe1-issue-on-T4160RDB-64B/m-p/854563#M2887</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Fine.&lt;/P&gt;&lt;P&gt;Then you have to provide additional information:&lt;/P&gt;&lt;P&gt;1) complete processor connection schematics as searchable PDF&lt;/P&gt;&lt;P&gt;2) measured frequencies of all SerDes reference clocks&lt;/P&gt;&lt;P&gt;3) Which EP device is used?&lt;/P&gt;&lt;P&gt;4) How the EP device is connected?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 14 Mar 2019 05:20:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/PCIe1-issue-on-T4160RDB-64B/m-p/854563#M2887</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2019-03-14T05:20:39Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe1 issue on T460RDB-64B</title>
      <link>https://community.nxp.com/t5/T-Series/PCIe1-issue-on-T4160RDB-64B/m-p/854564#M2888</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please find the attachment for Processor connection schematic.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;VinothS&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 14 Mar 2019 05:32:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/PCIe1-issue-on-T4160RDB-64B/m-p/854564#M2888</guid>
      <dc:creator>vinothkumars</dc:creator>
      <dc:date>2019-03-14T05:32:26Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe1 issue on T4160RDB-64B</title>
      <link>https://community.nxp.com/t5/T-Series/PCIe1-issue-on-T4160RDB-64B/m-p/854565#M2889</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;2) measured frequencies of all SerDes reference clocks&lt;/P&gt;&lt;P&gt;3) Which EP device is used?&lt;/P&gt;&lt;P&gt;4) How the EP device is connected?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 14 Mar 2019 05:51:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/PCIe1-issue-on-T4160RDB-64B/m-p/854565#M2889</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2019-03-14T05:51:26Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe1 issue on T4160RDB-64B</title>
      <link>https://community.nxp.com/t5/T-Series/PCIe1-issue-on-T4160RDB-64B/m-p/854566#M2890</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Ufedor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Serdes1 Frequency -&amp;nbsp; 100MHz&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Serdes2 Frequency - 156.25MHz&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Serdes3 Frequency - 100MHz&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Serdes4 Frequency - 100MHZ&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;EP device is PCI switch&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Regards, VinothS&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 14 Mar 2019 13:27:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/PCIe1-issue-on-T4160RDB-64B/m-p/854566#M2890</guid>
      <dc:creator>vinothkumars</dc:creator>
      <dc:date>2019-03-14T13:27:50Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe1 issue on T4160RDB-64B</title>
      <link>https://community.nxp.com/t5/T-Series/PCIe1-issue-on-T4160RDB-64B/m-p/854567#M2891</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Required additional information:&lt;/P&gt;&lt;P&gt;1) complete processor connection schematics as searchable PDF to check PCIe connection and SerDes powering&lt;/P&gt;&lt;P&gt;5) read the&amp;nbsp;PEX control/status register 0 (CSR0) several times and provide values&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 14 Mar 2019 14:13:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/PCIe1-issue-on-T4160RDB-64B/m-p/854567#M2891</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2019-03-14T14:13:31Z</dc:date>
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